ZHCSFY7B January 2017 – December 2021 ADS58J64
PRODUCTION DATA
The ADS58J64 is a quad-channel device with a complex digital down-converter (DDC) and digital decimation to allow flexible signal processing to suit different usage cases. Each channel is composed of two interleaved analog-to-digital converters (ADCs) sampling at half the input clock rate. The 2x interleaved data are decimated by 2 to provide a processing gain of 3 dB. The decimation filter can be configured as low pass (default) or high pass. The half-rate (with regards to the input clock) data are available on the output, in burst mode (DDC mode = 8) as a stream of high (14-bit) and low (9-bit) resolution samples. Burst mode can be enabled by device programming along with other options (such as the number of high- and low-resolution samples, and trigger mode as either automatic or pin-controlled). In default mode, the device operates in DDC mode 0, where the input is mixed with a constant frequency of –fS / 4 and is given out as complex IQ. The different operational modes modes of the ADS58J64 are listed in Table 7-1.