ZHCSJX5 June   2019 ADS7028

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      ADS7028 方框图和 应用
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer and ADC
      2. 8.3.2  Reference
      3. 8.3.3  ADC Transfer Function
      4. 8.3.4  ADC Offset Calibration
      5. 8.3.5  Programmable Averaging Filter
      6. 8.3.6  CRC on Data Interface
      7. 8.3.7  General-Purpose I/Os
      8. 8.3.8  Oscillator and Timing Control
      9. 8.3.9  Output Data Format
      10. 8.3.10 Zero-Crossing-Detect Module
      11. 8.3.11 Digital Window Comparator
        1. 8.3.11.1 Interrupts From Digital Inputs
        2. 8.3.11.2 Triggering Digital Outputs With Alert and ZCD
          1. 8.3.11.2.1 Triggering Digital Outputs on Alerts
            1. 8.3.11.2.1.1 Trigger
            2. 8.3.11.2.1.2 Output Value
          2. 8.3.11.2.2 Changing Digital Outputs Synchronous to ZCD
      12. 8.3.12 Root-Mean-Square Module
      13. 8.3.13 Minimum, Maximum, and Latest Data Registers
      14. 8.3.14 Device Programming
        1. 8.3.14.1 Enhanced-SPI Interface
        2. 8.3.14.2 Register Read/Write Operation
          1. 8.3.14.2.1 Register Write
          2. 8.3.14.2.2 Register Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Power-Up and Reset
      2. 8.4.2 Manual Mode
      3. 8.4.3 On-the-Fly Mode
      4. 8.4.4 Auto-Sequence Mode
      5. 8.4.5 Autonomous Mode
    5. 8.5 ADS7028 Registers
      1. 8.5.1   SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
        1. Table 11. SYSTEM_STATUS Register Field Descriptions
      2. 8.5.2   GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
        1. Table 12. GENERAL_CFG Register Field Descriptions
      3. 8.5.3   DATA_CFG Register (Address = 0x2) [reset = 0x0]
        1. Table 13. DATA_CFG Register Field Descriptions
      4. 8.5.4   OSR_CFG Register (Address = 0x3) [reset = 0x0]
        1. Table 14. OSR_CFG Register Field Descriptions
      5. 8.5.5   OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
        1. Table 15. OPMODE_CFG Register Field Descriptions
      6. 8.5.6   PIN_CFG Register (Address = 0x5) [reset = 0x0]
        1. Table 16. PIN_CFG Register Field Descriptions
      7. 8.5.7   GPIO_CFG Register (Address = 0x7) [reset = 0x0]
        1. Table 17. GPIO_CFG Register Field Descriptions
      8. 8.5.8   GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
        1. Table 18. GPO_DRIVE_CFG Register Field Descriptions
      9. 8.5.9   GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
        1. Table 19. GPO_OUTPUT_VALUE Register Field Descriptions
      10. 8.5.10  GPI_VALUE Register (Address = 0xD) [reset = 0x0]
        1. Table 20. GPI_VALUE Register Field Descriptions
      11. 8.5.11  ZCD_BLANKING_CFG Register (Address = 0xF) [reset = 0x0]
        1. Table 21. ZCD_BLANKING_CFG Register Field Descriptions
      12. 8.5.12  SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
        1. Table 22. SEQUENCE_CFG Register Field Descriptions
      13. 8.5.13  CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
        1. Table 23. CHANNEL_SEL Register Field Descriptions
      14. 8.5.14  AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
        1. Table 24. AUTO_SEQ_CH_SEL Register Field Descriptions
      15. 8.5.15  ALERT_CH_SEL Register (Address = 0x14) [reset = 0x0]
        1. Table 25. ALERT_CH_SEL Register Field Descriptions
      16. 8.5.16  ALERT_MAP Register (Address = 0x16) [reset = 0x0]
        1. Table 26. ALERT_MAP Register Field Descriptions
      17. 8.5.17  ALERT_PIN_CFG Register (Address = 0x17) [reset = 0x0]
        1. Table 27. ALERT_PIN_CFG Register Field Descriptions
      18. 8.5.18  EVENT_FLAG Register (Address = 0x18) [reset = 0x0]
        1. Table 28. EVENT_FLAG Register Field Descriptions
      19. 8.5.19  EVENT_HIGH_FLAG Register (Address = 0x1A) [reset = 0x0]
        1. Table 29. EVENT_HIGH_FLAG Register Field Descriptions
      20. 8.5.20  EVENT_LOW_FLAG Register (Address = 0x1C) [reset = 0x0]
        1. Table 30. EVENT_LOW_FLAG Register Field Descriptions
      21. 8.5.21  EVENT_RGN Register (Address = 0x1E) [reset = 0x0]
        1. Table 31. EVENT_RGN Register Field Descriptions
      22. 8.5.22  HYSTERESIS_CH0 Register (Address = 0x20) [reset = 0xF0]
        1. Table 32. HYSTERESIS_CH0 Register Field Descriptions
      23. 8.5.23  HIGH_TH_CH0 Register (Address = 0x21) [reset = 0xFF]
        1. Table 33. HIGH_TH_CH0 Register Field Descriptions
      24. 8.5.24  EVENT_COUNT_CH0 Register (Address = 0x22) [reset = 0x0]
        1. Table 34. EVENT_COUNT_CH0 Register Field Descriptions
      25. 8.5.25  LOW_TH_CH0 Register (Address = 0x23) [reset = 0x0]
        1. Table 35. LOW_TH_CH0 Register Field Descriptions
      26. 8.5.26  HYSTERESIS_CH1 Register (Address = 0x24) [reset = 0xF0]
        1. Table 36. HYSTERESIS_CH1 Register Field Descriptions
      27. 8.5.27  HIGH_TH_CH1 Register (Address = 0x25) [reset = 0xFF]
        1. Table 37. HIGH_TH_CH1 Register Field Descriptions
      28. 8.5.28  EVENT_COUNT_CH1 Register (Address = 0x26) [reset = 0x0]
        1. Table 38. EVENT_COUNT_CH1 Register Field Descriptions
      29. 8.5.29  LOW_TH_CH1 Register (Address = 0x27) [reset = 0x0]
        1. Table 39. LOW_TH_CH1 Register Field Descriptions
      30. 8.5.30  HYSTERESIS_CH2 Register (Address = 0x28) [reset = 0xF0]
        1. Table 40. HYSTERESIS_CH2 Register Field Descriptions
      31. 8.5.31  HIGH_TH_CH2 Register (Address = 0x29) [reset = 0xFF]
        1. Table 41. HIGH_TH_CH2 Register Field Descriptions
      32. 8.5.32  EVENT_COUNT_CH2 Register (Address = 0x2A) [reset = 0x0]
        1. Table 42. EVENT_COUNT_CH2 Register Field Descriptions
      33. 8.5.33  LOW_TH_CH2 Register (Address = 0x2B) [reset = 0x0]
        1. Table 43. LOW_TH_CH2 Register Field Descriptions
      34. 8.5.34  HYSTERESIS_CH3 Register (Address = 0x2C) [reset = 0xF0]
        1. Table 44. HYSTERESIS_CH3 Register Field Descriptions
      35. 8.5.35  HIGH_TH_CH3 Register (Address = 0x2D) [reset = 0xFF]
        1. Table 45. HIGH_TH_CH3 Register Field Descriptions
      36. 8.5.36  EVENT_COUNT_CH3 Register (Address = 0x2E) [reset = 0x0]
        1. Table 46. EVENT_COUNT_CH3 Register Field Descriptions
      37. 8.5.37  LOW_TH_CH3 Register (Address = 0x2F) [reset = 0x0]
        1. Table 47. LOW_TH_CH3 Register Field Descriptions
      38. 8.5.38  HYSTERESIS_CH4 Register (Address = 0x30) [reset = 0xF0]
        1. Table 48. HYSTERESIS_CH4 Register Field Descriptions
      39. 8.5.39  HIGH_TH_CH4 Register (Address = 0x31) [reset = 0xFF]
        1. Table 49. HIGH_TH_CH4 Register Field Descriptions
      40. 8.5.40  EVENT_COUNT_CH4 Register (Address = 0x32) [reset = 0x0]
        1. Table 50. EVENT_COUNT_CH4 Register Field Descriptions
      41. 8.5.41  LOW_TH_CH4 Register (Address = 0x33) [reset = 0x0]
        1. Table 51. LOW_TH_CH4 Register Field Descriptions
      42. 8.5.42  HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0]
        1. Table 52. HYSTERESIS_CH5 Register Field Descriptions
      43. 8.5.43  HIGH_TH_CH5 Register (Address = 0x35) [reset = 0xFF]
        1. Table 53. HIGH_TH_CH5 Register Field Descriptions
      44. 8.5.44  EVENT_COUNT_CH5 Register (Address = 0x36) [reset = 0x0]
        1. Table 54. EVENT_COUNT_CH5 Register Field Descriptions
      45. 8.5.45  LOW_TH_CH5 Register (Address = 0x37) [reset = 0x0]
        1. Table 55. LOW_TH_CH5 Register Field Descriptions
      46. 8.5.46  HYSTERESIS_CH6 Register (Address = 0x38) [reset = 0xF0]
        1. Table 56. HYSTERESIS_CH6 Register Field Descriptions
      47. 8.5.47  HIGH_TH_CH6 Register (Address = 0x39) [reset = 0xFF]
        1. Table 57. HIGH_TH_CH6 Register Field Descriptions
      48. 8.5.48  EVENT_COUNT_CH6 Register (Address = 0x3A) [reset = 0x0]
        1. Table 58. EVENT_COUNT_CH6 Register Field Descriptions
      49. 8.5.49  LOW_TH_CH6 Register (Address = 0x3B) [reset = 0x0]
        1. Table 59. LOW_TH_CH6 Register Field Descriptions
      50. 8.5.50  HYSTERESIS_CH7 Register (Address = 0x3C) [reset = 0xF0]
        1. Table 60. HYSTERESIS_CH7 Register Field Descriptions
      51. 8.5.51  HIGH_TH_CH7 Register (Address = 0x3D) [reset = 0xFF]
        1. Table 61. HIGH_TH_CH7 Register Field Descriptions
      52. 8.5.52  EVENT_COUNT_CH7 Register (Address = 0x3E) [reset = 0x0]
        1. Table 62. EVENT_COUNT_CH7 Register Field Descriptions
      53. 8.5.53  LOW_TH_CH7 Register (Address = 0x3F) [reset = 0x0]
        1. Table 63. LOW_TH_CH7 Register Field Descriptions
      54. 8.5.54  MAX_CH0_LSB Register (Address = 0x60) [reset = 0x0]
        1. Table 64. MAX_CH0_LSB Register Field Descriptions
      55. 8.5.55  MAX_CH0_MSB Register (Address = 0x61) [reset = 0x0]
        1. Table 65. MAX_CH0_MSB Register Field Descriptions
      56. 8.5.56  MAX_CH1_LSB Register (Address = 0x62) [reset = 0x0]
        1. Table 66. MAX_CH1_LSB Register Field Descriptions
      57. 8.5.57  MAX_CH1_MSB Register (Address = 0x63) [reset = 0x0]
        1. Table 67. MAX_CH1_MSB Register Field Descriptions
      58. 8.5.58  MAX_CH2_LSB Register (Address = 0x64) [reset = 0x0]
        1. Table 68. MAX_CH2_LSB Register Field Descriptions
      59. 8.5.59  MAX_CH2_MSB Register (Address = 0x65) [reset = 0x0]
        1. Table 69. MAX_CH2_MSB Register Field Descriptions
      60. 8.5.60  MAX_CH3_LSB Register (Address = 0x66) [reset = 0x0]
        1. Table 70. MAX_CH3_LSB Register Field Descriptions
      61. 8.5.61  MAX_CH3_MSB Register (Address = 0x67) [reset = 0x0]
        1. Table 71. MAX_CH3_MSB Register Field Descriptions
      62. 8.5.62  MAX_CH4_LSB Register (Address = 0x68) [reset = 0x0]
        1. Table 72. MAX_CH4_LSB Register Field Descriptions
      63. 8.5.63  MAX_CH4_MSB Register (Address = 0x69) [reset = 0x0]
        1. Table 73. MAX_CH4_MSB Register Field Descriptions
      64. 8.5.64  MAX_CH5_LSB Register (Address = 0x6A) [reset = 0x0]
        1. Table 74. MAX_CH5_LSB Register Field Descriptions
      65. 8.5.65  MAX_CH5_MSB Register (Address = 0x6B) [reset = 0x0]
        1. Table 75. MAX_CH5_MSB Register Field Descriptions
      66. 8.5.66  MAX_CH6_LSB Register (Address = 0x6C) [reset = 0x0]
        1. Table 76. MAX_CH6_LSB Register Field Descriptions
      67. 8.5.67  MAX_CH6_MSB Register (Address = 0x6D) [reset = 0x0]
        1. Table 77. MAX_CH6_MSB Register Field Descriptions
      68. 8.5.68  MAX_CH7_LSB Register (Address = 0x6E) [reset = 0x0]
        1. Table 78. MAX_CH7_LSB Register Field Descriptions
      69. 8.5.69  MAX_CH7_MSB Register (Address = 0x6F) [reset = 0x0]
        1. Table 79. MAX_CH7_MSB Register Field Descriptions
      70. 8.5.70  MIN_CH0_LSB Register (Address = 0x80) [reset = 0xFF]
        1. Table 80. MIN_CH0_LSB Register Field Descriptions
      71. 8.5.71  MIN_CH0_MSB Register (Address = 0x81) [reset = 0xFF]
        1. Table 81. MIN_CH0_MSB Register Field Descriptions
      72. 8.5.72  MIN_CH1_LSB Register (Address = 0x82) [reset = 0xFF]
        1. Table 82. MIN_CH1_LSB Register Field Descriptions
      73. 8.5.73  MIN_CH1_MSB Register (Address = 0x83) [reset = 0xFF]
        1. Table 83. MIN_CH1_MSB Register Field Descriptions
      74. 8.5.74  MIN_CH2_LSB Register (Address = 0x84) [reset = 0xFF]
        1. Table 84. MIN_CH2_LSB Register Field Descriptions
      75. 8.5.75  MIN_CH2_MSB Register (Address = 0x85) [reset = 0xFF]
        1. Table 85. MIN_CH2_MSB Register Field Descriptions
      76. 8.5.76  MIN_CH3_LSB Register (Address = 0x86) [reset = 0xFF]
        1. Table 86. MIN_CH3_LSB Register Field Descriptions
      77. 8.5.77  MIN_CH3_MSB Register (Address = 0x87) [reset = 0xFF]
        1. Table 87. MIN_CH3_MSB Register Field Descriptions
      78. 8.5.78  MIN_CH4_LSB Register (Address = 0x88) [reset = 0xFF]
        1. Table 88. MIN_CH4_LSB Register Field Descriptions
      79. 8.5.79  MIN_CH4_MSB Register (Address = 0x89) [reset = 0xFF]
        1. Table 89. MIN_CH4_MSB Register Field Descriptions
      80. 8.5.80  MIN_CH5_LSB Register (Address = 0x8A) [reset = 0xFF]
        1. Table 90. MIN_CH5_LSB Register Field Descriptions
      81. 8.5.81  MIN_CH5_MSB Register (Address = 0x8B) [reset = 0xFF]
        1. Table 91. MIN_CH5_MSB Register Field Descriptions
      82. 8.5.82  MIN_CH6_LSB Register (Address = 0x8C) [reset = 0xFF]
        1. Table 92. MIN_CH6_LSB Register Field Descriptions
      83. 8.5.83  MIN_CH6_MSB Register (Address = 0x8D) [reset = 0xFF]
        1. Table 93. MIN_CH6_MSB Register Field Descriptions
      84. 8.5.84  MIN_CH7_LSB Register (Address = 0x8E) [reset = 0xFF]
        1. Table 94. MIN_CH7_LSB Register Field Descriptions
      85. 8.5.85  MIN_CH7_MSB Register (Address = 0x8F) [reset = 0xFF]
        1. Table 95. MIN_CH7_MSB Register Field Descriptions
      86. 8.5.86  RECENT_CH0_LSB Register (Address = 0xA0) [reset = 0x0]
        1. Table 96. RECENT_CH0_LSB Register Field Descriptions
      87. 8.5.87  RECENT_CH0_MSB Register (Address = 0xA1) [reset = 0x0]
        1. Table 97. RECENT_CH0_MSB Register Field Descriptions
      88. 8.5.88  RECENT_CH1_LSB Register (Address = 0xA2) [reset = 0x0]
        1. Table 98. RECENT_CH1_LSB Register Field Descriptions
      89. 8.5.89  RECENT_CH1_MSB Register (Address = 0xA3) [reset = 0x0]
        1. Table 99. RECENT_CH1_MSB Register Field Descriptions
      90. 8.5.90  RECENT_CH2_LSB Register (Address = 0xA4) [reset = 0x0]
        1. Table 100. RECENT_CH2_LSB Register Field Descriptions
      91. 8.5.91  RECENT_CH2_MSB Register (Address = 0xA5) [reset = 0x0]
        1. Table 101. RECENT_CH2_MSB Register Field Descriptions
      92. 8.5.92  RECENT_CH3_LSB Register (Address = 0xA6) [reset = 0x0]
        1. Table 102. RECENT_CH3_LSB Register Field Descriptions
      93. 8.5.93  RECENT_CH3_MSB Register (Address = 0xA7) [reset = 0x0]
        1. Table 103. RECENT_CH3_MSB Register Field Descriptions
      94. 8.5.94  RECENT_CH4_LSB Register (Address = 0xA8) [reset = 0x0]
        1. Table 104. RECENT_CH4_LSB Register Field Descriptions
      95. 8.5.95  RECENT_CH4_MSB Register (Address = 0xA9) [reset = 0x0]
        1. Table 105. RECENT_CH4_MSB Register Field Descriptions
      96. 8.5.96  RECENT_CH5_LSB Register (Address = 0xAA) [reset = 0x0]
        1. Table 106. RECENT_CH5_LSB Register Field Descriptions
      97. 8.5.97  RECENT_CH5_MSB Register (Address = 0xAB) [reset = 0x0]
        1. Table 107. RECENT_CH5_MSB Register Field Descriptions
      98. 8.5.98  RECENT_CH6_LSB Register (Address = 0xAC) [reset = 0x0]
        1. Table 108. RECENT_CH6_LSB Register Field Descriptions
      99. 8.5.99  RECENT_CH6_MSB Register (Address = 0xAD) [reset = 0x0]
        1. Table 109. RECENT_CH6_MSB Register Field Descriptions
      100. 8.5.100 RECENT_CH7_LSB Register (Address = 0xAE) [reset = 0x0]
        1. Table 110. RECENT_CH7_LSB Register Field Descriptions
      101. 8.5.101 RECENT_CH7_MSB Register (Address = 0xAF) [reset = 0x0]
        1. Table 111. RECENT_CH7_MSB Register Field Descriptions
      102. 8.5.102 RMS_CFG Register (Address = 0xC0) [reset = 0x0]
        1. Table 112. RMS_CFG Register Field Descriptions
      103. 8.5.103 RMS_LSB Register (Address = 0xC1) [reset = 0x0]
        1. Table 113. RMS_LSB Register Field Descriptions
      104. 8.5.104 RMS_MSB Register (Address = 0xC2) [reset = 0x0]
        1. Table 114. RMS_MSB Register Field Descriptions
      105. 8.5.105 GPO0_TRIG_EVENT_SEL Register (Address = 0xC3) [reset = 0x2]
        1. Table 115. GPO0_TRIG_EVENT_SEL Register Field Descriptions
      106. 8.5.106 GPO1_TRIG_EVENT_SEL Register (Address = 0xC5) [reset = 0x1]
        1. Table 116. GPO1_TRIG_EVENT_SEL Register Field Descriptions
      107. 8.5.107 GPO2_TRIG_EVENT_SEL Register (Address = 0xC7) [reset = 0x8]
        1. Table 117. GPO2_TRIG_EVENT_SEL Register Field Descriptions
      108. 8.5.108 GPO3_TRIG_EVENT_SEL Register (Address = 0xC9) [reset = 0x4]
        1. Table 118. GPO3_TRIG_EVENT_SEL Register Field Descriptions
      109. 8.5.109 GPO4_TRIG_EVENT_SEL Register (Address = 0xCB) [reset = 0x20]
        1. Table 119. GPO4_TRIG_EVENT_SEL Register Field Descriptions
      110. 8.5.110 GPO5_TRIG_EVENT_SEL Register (Address = 0xCD) [reset = 0x10]
        1. Table 120. GPO5_TRIG_EVENT_SEL Register Field Descriptions
      111. 8.5.111 GPO6_TRIG_EVENT_SEL Register (Address = 0xCF) [reset = 0x80]
        1. Table 121. GPO6_TRIG_EVENT_SEL Register Field Descriptions
      112. 8.5.112 GPO7_TRIG_EVENT_SEL Register (Address = 0xD1) [reset = 0x40]
        1. Table 122. GPO7_TRIG_EVENT_SEL Register Field Descriptions
      113. 8.5.113 GPO_VALUE_ZCD_CFG_CH0_CH3 Register (Address = 0xE3) [reset = 0x0]
        1. Table 123. GPO_VALUE_ZCD_CFG_CH0_CH3 Register Field Descriptions
      114. 8.5.114 GPO_VALUE_ZCD_CFG_CH4_CH7 Register (Address = 0xE4) [reset = 0x0]
        1. Table 124. GPO_VALUE_ZCD_CFG_CH4_CH7 Register Field Descriptions
      115. 8.5.115 GPO_ZCD_UPDATE_EN Register (Address = 0xE7) [reset = 0x0]
        1. Table 125. GPO_ZCD_UPDATE_EN Register Field Descriptions
      116. 8.5.116 GPO_TRIGGER_CFG Register (Address = 0xE9) [reset = 0x0]
        1. Table 126. GPO_TRIGGER_CFG Register Field Descriptions
      117. 8.5.117 GPO_VALUE_TRIG Register (Address = 0xEB) [reset = 0x0]
        1. Table 127. GPO_VALUE_TRIG Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Mixed-Channel Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Digital Input
          2. 9.2.1.2.2 Digital Open-Drain Output
      2. 9.2.2 Digital Push-Pull Output Configuration
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11.1 Layout Guidelines

Figure 142 shows a board layout example for the ADS7028. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the AVDD supply away from noise sources.

Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference voltage for the ADS7028. Place the decoupling capacitor (CREF) for AVDD close to the device AVDD and GND pins and connect CREF to the device pins with thick copper tracks.

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