The host must compute and append the appropriate 8-bit CRC to the command string in the same SPI frame (see Register Read With CRC). The ADC also computes the expected 8-bit CRC corresponding to the 24-bit payload received from the host and compares the calculated CRC code to the CRC received from the host. If a communication error is detected, the CRCERR_IN bit in the SYSTEM_STATUS register is set to 1b. The CRCERR_IN bit is set in the following scenarios:

• The SPI communication frame did not have 32 clocks exactly, corresponding to a 24-bit data payload and an 8-bit CRC.
• The CRC calculated by the ADC over the received 24-bit payload does not match with the corresponding 8-bit CRC received from the host.

If a CRC error is detected by the device, the command does not execute and the CRCERR_IN flag is set to 1b. ADC conversion data read and register read, with a valid CRC from the host, are still supported. The error condition can be detected, as listed in Table 7-5, by either status flags or by a register read. Further register writes to the device are blocked until CRCERR_IN flag is cleared to 0b. Register write operation, with valid CRC from the host, to the SYSTEM_STATUS and GENERAL_CFG registers is still supported.

The device can be configured to set all channels to analog inputs on detecting a CRC error by setting CH_RST bit to 1b. This would ensure that channels which were configured as digital outputs are not driven by the device when CRC error is detected. All channels will be reset as per the configuration in the PIN_CFG and GPIO_CFG registers when CRCERR_IN flag is cleared.

The device can be configured to abort further conversions in autonomous and turbo comparator modes (see the Autonomous Mode and Turbo Comparator Mode sections), on detecting a CRC error, by setting CONV_ON_ERR = 1b.