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ZHCSFM9 November 2016 ADS7049-Q1

PRODUCTION DATA.

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DCU|8
- MPDS050E

散热焊盘机械数据 (封装 | 引脚)

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6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

	MIN	MAX	UNIT
AVDD to GND	–0.3	3.9	V
DVDD to GND	–0.3	3.9	V
AINP to GND	–0.3	AVDD + 0.3	V
AINM to GND	–0.3	0.3	V
Digital input voltage to GND	–0.3	DVDD + 0.3	V
Storage temperature, T_stg	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
AVDD	Analog supply voltage range	2.35	3.6	V
DVDD	Digital supply voltage range	1.65	3.6	V
T_A	Operating free-air temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS7049-Q1	UNIT
		DCU (VSSOP)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	181.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	50.8	°C/W
R_θJB	Junction-to-board thermal resistance	73.9	°C/W
ψ_JT	Junction-to-top characterization parameter	1.0	°C/W
ψ_JB	Junction-to-board characterization parameter	73.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at T_A = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, f_SAMPLE = 2 MSPS, and V_AINM = 0 V (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
	Full-scale input voltage span⁽¹⁾			0		AVDD	V
	Absolute input voltage range	AINP to GND		–0.1		AVDD + 0.1	V
	Absolute input voltage range	AINM to GND		–0.1		0.1	V
C_S	Sampling capacitance				15		pF
SYSTEM PERFORMANCE
	Resolution				12		Bits
NMC	No missing codes			12			Bits
INL	Integral nonlinearity		AVDD = 3 V	–1	±0.5	1	LSB⁽²⁾
DNL	Differential nonlinearity		AVDD = 3 V	–0.99	±0.5	1	LSB
E_O	Offset error	Uncalibrated			±12		LSB
E_O	Offset error	Calibrated⁽⁶⁾	AVDD = 3 V	–3	±0.5	3	LSB
dV_OS/dT	Offset error drift with temperature				±5		ppm/°C
E_G	Gain error		AVDD = 3 V	–0.1	±0.05	0.1	%FS
	Gain error drift with temperature		No calibration		±2		ppm/°C
SAMPLING DYNAMICS
t_ACQ	Acquisition time			90			ns
	Maximum throughput rate		32-MHz SCLK, AVDD = 2.35 V to 3.6 V			2	MHz
DYNAMIC CHARACTERISTICS
SNR	Signal-to-noise ratio⁽⁴⁾		f_IN = 2 kHz, AVDD = 3 V	68	70		dB
THD	Total harmonic distortion⁽⁴⁾⁽³⁾		f_IN = 2 kHz, AVDD = 3 V		–80		dB
SINAD	Signal-to-noise and distortion⁽⁴⁾		f_IN = 2 kHz, AVDD = 3 V	67.5	69.5		dB
SFDR	Spurious-free dynamic range⁽⁴⁾		f_IN = 2 kHz, AVDD = 3 V		80		dB
BW_(fp)	Full-power bandwidth		At –3 dB, AVDD = 3 V		25		MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
V_IH	High-level input voltage⁽⁵⁾			0.65 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage⁽⁵⁾			–0.3		0.35 × DVDD	V
V_OH	High-level output voltage⁽⁵⁾		At I_source = 500 µA	0.8 × DVDD		DVDD	V
V_OH	High-level output voltage⁽⁵⁾		At I_source = 2 mA	DVDD – 0.45		DVDD	V
V_OL	Low-level output voltage⁽⁵⁾		At I_sink = 500 µA	0		0.2 × DVDD	V
V_OL	Low-level output voltage⁽⁵⁾		At I_sink = 2 mA	0		0.45	V
POWER-SUPPLY REQUIREMENTS
AVDD	Analog supply voltage			2.35	3	3.6	V
DVDD	Digital I/O supply voltage			1.65	3	3.6	V
I_AVDD	Analog supply current		At 2 MSPS with AVDD = 3 V		380	460	µA
I_DVDD	Digital supply current		AVDD = 3 V, no load, no transitions		10		µA
P_D	Power dissipation		At 2 MSPS with AVDD = 3 V		1.14	1.38	mW

(1) Ideal input span; does not include gain or offset error.

(2) LSB means least significant bit.

(3) Calculated on the first nine harmonics of the input frequency.

(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.

(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Digital Voltage Levels section for more details.

(6) See the Offset Calibration section for more details.

6.6 Timing Requirements

all specifications are at T_A = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and C_LOAD on SDO = 20 pF (unless otherwise specified)

		MIN	MAX	UNIT
t_ACQ	Acquisition time	90		ns
f_SCLK	SCLK frequency	0.016	32	MHz
t_SCLK	SCLK period	31.25		ns
t_{PH_CK}	SCLK high time	0.45	0.55	t_SCLK
t_{PL_CK}	SCLK low time	0.45	0.55	t_SCLK
t_{PH_CS}	CS high time	30		ns
t_{SU_CSCK}	Setup time: CS falling to SCLK falling	12		ns
t_{D_CKCS}	Delay time: last SCLK falling to CS rising	10		ns

6.7 Switching Characteristics

all specifications are at T_A = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and C_LOAD on SDO = 20 pF (unless otherwise specified)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_THROUGHPUT	Throughput				2	MSPS
t_CYCLE	Cycle time		0.5			µs
t_CONV	Conversion time			12.5 × t_SCLK + t_{SU_CSCK}		ns
t_{DV_CSDO}	Delay time: CS falling to data enable				10	ns
t_{D_CKDO}	Delay time: SCLK falling to (next) data valid on DOUT	AVDD = 2.35 V to 3.6 V			25	ns
t_{DZ_CSDO}	Delay time: CS rising to DOUT going to tri-state		5			ns