ZHCSH54 December 2017 ADS7054
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
6 Specifications
6.1 Absolute Maximum Ratings(1)
| MIN | MAX | UNIT | |
|---|---|---|---|
| AVDD to GND | –0.3 | 3.9 | V |
| DVDD to GND | –0.3 | 3.9 | V |
| AINP to GND | –0.3 | AVDD + 0.3 | V |
| AINM to GND | –0.3 | AVDD + 0.3 | V |
| Input current to any pin except supply pins | –10 | 10 | mA |
| Digital input voltage to GND | –0.3 | DVDD + 0.3 | V |
| Storage temperature, Tstg | –60 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| AVDD | Analog supply voltage range | 1.65 | 3.3 | 3.6 | V |
| DVDD | Digital supply voltage range | 1.65 | 1.8 | 3.6 | V |
| TA | Operating free-air temperature | –40 | 25 | 125 | °C |
6.4 Thermal Information
| THERMAL METRIC(1) | ADS7054 | UNIT | |
|---|---|---|---|
| RUG (X2QFN) | |||
| 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 177.5 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 51.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 76.7 | °C/W |
| ψJT | Junction-to-top characterization parameter | 1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 76.7 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, fsample = 1 MSPS, and VCM = 1.65 V (unless otherwise noted); minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ANALOG INPUT | ||||||
| Full-scale input voltage span(1) | –AVDD | AVDD | V | |||
| Absolute input voltage range | AINP to GND | –0.1 | AVDD + 0.1 | V | ||
| AINM to GND | –0.1 | AVDD + 0.1 | ||||
| Common-mode voltage | (AINP + AINM) / 2 | (AVDD / 2) – 0.1 | (AVDD / 2) + 0.1 | V | ||
| CS | Sampling capacitance | 16 | pF | |||
| SYSTEM PERFORMANCE | ||||||
| Resolution | 14 | Bits | ||||
| NMC | No missing codes | 14 | Bits | |||
| INL(8) | Integral nonlinearity | –3 | ±0.9 | 3 | LSB(2) | |
| DNL | Differential nonlinearity | –0.99 | ±0.5 | 1 | LSB | |
| EO(8) | Offset error | After calibration(7) | –6 | ±1 | 6 | LSB |
| dVOS/dT | Offset error drift with temperature | 1.75 | ppm/°C | |||
| EG(8) | Gain error | –0.1 | ±0.01 | 0.1 | %FS | |
| Gain error drift with temperature | 0.5 | ppm/°C | ||||
| SAMPLING DYNAMICS | ||||||
| tCONV | Conversion time | 18 × tSCLK | ns | |||
| tACQ | Acquisition time | 230 | ns | |||
| fSAMPLE | Maximum throughput rate | 24-MHz SCLK, AVDD = 1.65 V to 3.6 V | 1 | MHz | ||
| Aperture delay | 3 | ns | ||||
| Aperture jitter, RMS | 12 | ps | ||||
| DYNAMIC CHARACTERISTICS | ||||||
| SNR | Signal-to-noise ratio(4) | AVDD = 3.3 V, fIN = 2 kHz | 76 | 79.6 | dB | |
| AVDD = 2.5 V, fIN = 2 kHz | 78.5 | |||||
| THD | Total harmonic distortion(4)(3) | fIN = 2 kHz | –92 | dB | ||
| fIN = 100 kHz | –90.8 | |||||
| fIN = 200 kHz | –90 | |||||
| SINAD | Signal-to-noise and distortion(4) | fIN = 2 kHz | 76 | 79.4 | dB | |
| fIN = 100 kHz | 78.7 | |||||
| fIN = 200 kHz | 78.5 | |||||
| SFDR | Spurious-free dynamic range(4) | fIN = 2 kHz | 92 | dB | ||
| fIN = 100 kHz | 91.7 | |||||
| fIN = 200 kHz | 90 | |||||
| BW(fp) | Full-power bandwidth | At –3 dB | 200 | MHz | ||
| DIGITAL INPUT/OUTPUT (CMOS Logic Family) | ||||||
| VIH | High-level input voltage(5) | 0.65 DVDD | DVDD + 0.3 | V | ||
| VIL | Low-level input voltage(5) | –0.3 | 0.35 DVDD | V | ||
| VOH | High-level output voltage(5) | At Isource = 500 µA | 0.8 DVDD | DVDD | V | |
| At Isource = 2 mA | DVDD – 0.45 | DVDD | ||||
| VOL | Low-level output voltage(5) | At Isink = 500 µA | 0 | 0.2 DVDD | V | |
| At Isink = 2 mA | 0 | 0.45 | ||||
| POWER-SUPPLY REQUIREMENTS | ||||||
| AVDD | Analog supply voltage | 1.65 | 3 | 3.6 | V | |
| DVDD | Digital I/O supply voltage | 1.65 | 3 | 3.6 | V | |
| IAVDD | Analog supply current | AVDD = 3.3 V, fSAMPLE = 1 MSPS | 450 | 560 | µA | |
| AVDD = 3.3 V, fSAMPLE = 100 kSPS | 47 | 55 | ||||
| AVDD = 3.3 V, fSAMPLE = 10 kSPS | 5 | |||||
| AVDD = 1.8 V, fSAMPLE = 1 MSPS | 230 | |||||
| Static current with CS and SCLK high | 0.02 | |||||
| IDVDD | Digital supply current | DVDD = 1.8 V, CSDO = 20 pF, output code = 2AAAh(6) |
250 | µA | ||
| DVDD = 1.8 V, static current with CS and SCLK high | 0.01 | |||||
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Calculated on the first nine harmonics of the input frequency.
(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise noted.
(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Parameter Measurement Information section for details.
(6) See the Estimating Digital Power Consumption section for details.
(7) See the OFFCAL State section for details.
6.6 Timing Requirements
all specifications are at AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted); minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| tCLK | Time period of SCLK | 41.66 | ns | ||
| tsu_CSCK | Setup time: CS falling edge to SCLK falling edge | 7 | ns | ||
| tht_CKCS | Hold time: SCLK rising edge to CS rising edge | 8 | ns | ||
| tph_CK | SCLK high time | 0.45 | 0.55 | tSCLK | |
| tpl_CK | SCLK low time | 0.45 | 0.55 | tSCLK | |
| tph_CS | CS high time | 15 | ns | ||
6.7 Switching Characteristics
all specifications are at AVDD = 1.65 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted); minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tCYCLE(1) | Cycle time | 1000 | ns | |||
| tCONV | Conversion time | 18 × tSCLK | ns | |||
| tden_CSDO | Delay time: CS falling edge to data enable | 6.5 | ns | |||
| td_CKDO | Delay time: SCLK rising edge to (next) data valid on SDO | 10 | ns | |||
| tht_CKDO | SCLK rising edge to current data invalid | 2.5 | ns | |||
| tdz_CSDO | Delay time: CS rising edge to SDO going to tri-state | 5.5 | ns | |||
(1) tCYCLE = 1 / fSAMPLE.
Figure 1. Serial Transfer Frame
Figure 2. Timing Specifications
6.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fsample = 1 MSPS (unless otherwise noted)
| SNR = 80.6 dB, THD = –91.6 dB, ENOB = 13.0 bits |
| SNR = 76.6dB, THD = –90.6 dB, fIN = 200 kHz |
| VIN = 0 (differential) |
| SNR = 78.5 dB, THD = –89.5 dB, fIN = 100 kHz |
| CS = DVDD |
