ZHCSG66 March   2017 ADS7056

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Reference
      3. 8.3.3 ADC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 ACQ State
      2. 8.4.2 CNV State
      3. 8.4.3 OFFCAL State
        1. 8.4.3.1 Offset Calibration on Power-Up
        2. 8.4.3.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Supply Data Acquisition With the ADS7056
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Low Distortion Charge Kickback Filter Design
          2. 9.2.1.2.2 Input Amplifier Selection
          3. 9.2.1.2.3 Reference Circuit
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High Bandwidth (1 MHz) Data Acquisition With the ADS7056
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 14-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Optimizing Power Consumed by the Device
      1. 10.2.1 Estimating Digital Power Consumption
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RUG|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
AVDD to GND –0.3 3.9 V
DVDD to GND –0.3 3.9 V
AINP to GND –0.3 AVDD + 0.3 V
AINM to GND –0.3 0.3 V
Input current to any pin except supply pins –10 10 mA
Digital input voltage to GND –0.3 DVDD + 0.3 V
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage range 2.35 3 3.6 V
DVDD Digital supply voltage range 1.65 1.8 3.6 V
TA Operating free-air temperature –40 25 125 °C

6.4 Thermal Information

THERMAL METRIC(1) ADS7056 UNIT
RUG (X2QFN)
8 PINS
RθJA Junction-to-ambient thermal resistance 177.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 51.5 °C/W
RθJB Junction-to-board thermal resistance 76.7 °C/W
ψJT Junction-to-top characterization parameter 1 °C/W
ψJB Junction-to-board characterization parameter 76.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at AVDD = 3.3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 2.5 MSPS, and VAINM = 0 V (unless otherwise noted); minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span(1) 0 AVDD V
Absolute input voltage range AINP to GND –0.1 AVDD + 0.1 V
AINM to GND –0.1 0.1
CS Sampling capacitance 16 pF
SYSTEM PERFORMANCE
Resolution 14 Bits
NMC No missing codes 14 Bits
INL(8) Integral nonlinearity –3 ±2 3 LSB(2)
DNL Differential nonlinearity –0.99 ±0.5 1 LSB
EO (8) Offset error After calibration(7) –6 ±2.5 6 LSB
dVOS/dT Offset error drift with temperature 1.75 ppm/°C
EG(8) Gain error –0.1 ±0.01 0.1 %FS
Gain error drift with temperature 0.5 ppm/°C
SAMPLING DYNAMICS
tCONV Conversion time 18 × tSCLK ns
tACQ Acquisition time 95 ns
fSAMPLE Maximum throughput rate 60-MHz SCLK, AVDD = 2.35 V to 3.6 V 2.5 MHz
Aperture delay 3 ns
Aperture jitter, RMS 12 ps
DYNAMIC CHARACTERISTICS
SNR Signal-to-noise ratio(4) AVDD = 3.3 V 72 74.9 dB
AVDD = 2.5 V 73.7
THD Total harmonic distortion(4)(3) fIN = 2 kHz –85 dB
fIN = 250 kHz –84.8
fIN = 1000 kHz –84.5
SINAD Signal-to-noise and distortion(4) fIN = 2 kHz 71.75 74.5 dB
fIN = 250 kHz 73.7
fIN = 1000 kHz 73.7
SFDR Spurious-free dynamic range(4) fIN = 2 kHz 89.8 dB
fIN = 250 kHz 88
fIN = 1000 kHz 87.5
BW(fp) Full-power bandwidth At –3 dB 200 MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH High-level input voltage(5) 0.65 DVDD DVDD + 0.3 V
VIL Low-level input voltage(5) –0.3 0.35 DVDD V
VOH High-level output voltage(5) At Isource = 500 µA 0.8 DVDD DVDD V
At Isource = 2 mA DVDD – 0.45 DVDD
VOL Low-level output voltage(5) At Isink = 500 µA 0 0.2 DVDD V
At Isink = 2 mA 0 0.45
POWER-SUPPLY REQUIREMENTS
AVDD Analog supply voltage 2.35 3 3.6 V
DVDD Digital I/O supply voltage 1.65 3 3.6 V
IAVDD Analog supply current AVDD = 3.3 V, fSAMPLE = 2.5 MSPS 1050 1250 µA
AVDD = 3.3 V, fSAMPLE = 100 kSPS 48 50
AVDD = 3.3 V, fSAMPLE = 10 kSPS 5
AVDD = 2.5 V, fSAMPLE = 2.5 MSPS 750
Static current with CS and SCLK high 0.02
IDVDD Digital supply current DVDD = 1.8 V, CSDO = 20 pF,
output code = 2AAAh(6)		 630 µA
DVDD = 1.8 V, static current with CS and SCLK high 0.01
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Calculated on the first nine harmonics of the input frequency.
(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise noted.
(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Parameter Measurement Information section for details.
(6) See the Estimating Digital Power Consumption section for details.
(7) See the OFFCAL State section for details.
(8) See Figure 32, Figure 33, and Figure 34 for statistical distribution data for INL, offset error, and gain error.

6.6 Timing Requirements

all specifications are at AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted); minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
MIN TYP MAX UNIT
tCLK Time period of SCLK 16.66 ns
tsu_CSCK Setup time: CS falling edge to SCLK falling edge 7 ns
tht_CKCS Hold time: SCLK rising edge to CS rising edge 8 ns
tph_CK SCLK high time 0.45 0.55 tSCLK
tpl_CK SCLK low time 0.45 0.55 tSCLK
tph_CS CS high time 15 ns

6.7 Switching Characteristics

all specifications are at AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD-SDO = 20 pF (unless otherwise noted); minimum and maximum values for TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tCYCLE(1) Cycle time 400 ns
tCONV Conversion time 18 × tSCLK ns
tden_CSDO Delay time: CS falling edge to data enable 6.5 ns
td_CKDO Delay time: SCLK rising edge to (next) data valid on SDO 10 ns
tht_CKDO SCLK rising edge to current data invalid 2.5
tdz_CSDO Delay time: CS rising edge to SDO going to tri-state 5.5 ns
(1) tCYCLE = 1 / fSAMPLE.
ADS7056 tim_spi_data_revB_sbas769.gif Figure 1. Serial Transfer Frame
ADS7056 tim_spi_specs_sbas769.gif Figure 2. Timing Specifications

6.8 Typical Characteristics

at TA = 25°C, AVDD = 3.3 V, DVDD = 1.8 V, fIN = 2 kHz, and fSample = 2.5 MSPS (unless otherwise noted)
ADS7056 D001_SBAS769.gif
SNR = 75.2 dB, THD = –90.25 dB, ENOB = 12.18 bits
Figure 3. Typical FFT
ADS7056 D003_SBAS769.gif
SNR = 74.2 dB, THD = –90.25 dB, fIN = 500 kHz
Figure 5. Typical FFT
ADS7056 D005_SBAS769.gif
Figure 7. SNR and SINAD vs Temperature
ADS7056 D007_SBAS769.gif
Figure 9. SNR and SINAD vs Reference Voltage (AVDD)
ADS7056 D009_SBAS769.gif
Figure 11. SFDR vs Temperature
ADS7056 D011_SBAS769.gif
Figure 13. SFDR vs Input Frequency
ADS7056 D013_SBAS769.gif
Figure 15. SFDR vs Reference Voltage (AVDD)
ADS7056 D015_SBAS769.gif
Figure 17. Offset vs Temperature
ADS7056 D017_SBAS769.gif
Figure 19. Gain Error vs Temperature
ADS7056 D020_SBAS769.gif
Figure 21. Typical INL
ADS7056 D022_SBAS769.gif
AVDD = 2.35 V
Figure 23. Typical INL
ADS7056 D024_SBAS769.gif
Figure 25. DNL vs Reference Voltage
ADS7056 D026_SBAS769.gif
Figure 27. INL vs Reference Voltage
ADS7056 D028_SBAS769.gif
Figure 29. AVDD Current vs Throughput
ADS7056 D030_SBAS769.gif
CS = DVDD
Figure 31. Static AVDD Current vs Temperature
ADS7056 sbas769_typical_offset_error_distribution.gif
Figure 33. Typical Offset Error Distribution
ADS7056 D002_SBAS769.gif
SNR = 74.3 dB, THD = –87.9 dB, fIN = 250 kHz
Figure 4. Typical FFT
ADS7056 D004_SBAS769.gif
SNR = 73.9 dB, THD = –87.1 dB, fIN = 1000 kHz
Figure 6. Typical FFT
ADS7056 D006_SBAS769.gif
Figure 8. SNR and SINAD vs Input Frequency
ADS7056 D008_SBAS769.gif
Figure 10. THD vs Temperature
ADS7056 D010_SBAS769.gif
Figure 12. THD vs Input Frequency
ADS7056 D012_SBAS769.gif
Figure 14. THD vs Reference Voltage (AVDD)
ADS7056 D014_SBAS769.gif
Standard deviation of codes = 0.94 LSB, VIN = AVDD / 2
Figure 16. DC Input Histogram
ADS7056 D016_SBAS769.gif
Figure 18. Offset vs Reference Voltage (AVDD)
ADS7056 D019_SBAS769.gif
Figure 20. Typical DNL
ADS7056 D021_SBAS769.gif
AVDD = 2.35 V
Figure 22. Typical DNL
ADS7056 D023_SBAS769.gif
Figure 24. DNL vs Temperature
ADS7056 D025_SBAS769.gif
Figure 26. INL vs Temperature
ADS7056 D027_SBAS769.gif
Figure 28. AVDD Current vs Temperature
ADS7056 D029_SBAS769.gif
Figure 30. AVDD Current vs AVDD Voltage
ADS7056 sbas769_typical_inl_distribution.gif
Figure 32. Typical INL Distribution
ADS7056 sbas769_typical_gain_error_distribution.gif
Figure 34. Typical Gain Error Distribution
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