As illustrated in Figure 8-1, a filter capacitor (C_FLT) is connected from each input pin of the ADC to ground. This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. This capacitor must be a COG- or NPO-type. One method for determining the required amplifier bandwidth and the values of the RC charge-kickback filter is provided in this section. This optimization and more details on the math behind the component selection are covered in ADC Precision Labs.

The minimum bandwidth of the amplifier for driving the ADC can be computed using the settling accuracy (0.5 LSB) and settling time (acquisition time) information. Equation 4, Equation 5, Equation 6, and Equation 7 compute the unity-gain bandwidth (UGBW) of the amplifier.

Equation 4.

Equation 5.

Equation 6.

Equation 7.

Based on the result of Equation 7, select an amplifier that has more than 7-MHz UGBW. For this example, OPA325 is used.

The value of C_filt is computed in Equation 8 by taking 20 times the internal sample-and-hold capacitance. The factor of 20 is a rule of thumb that is intended to minimize the droop in voltage on the charge-bucket capacitor, C_filt, after the start of the acquisition period. The filter resistor, R_filt, is computed in Equation 9 using the op-amp time constant and C_filt. Equation 10 and Equation 11 compute the minimum and maximum R_filt values, respectively.

Equation 8.

The value of C_fllt can be approximated to the nearest standard value 680 pF.

Equation 9.

Equation 10.

Equation 11.