The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose inputs/outputs (GPIOs). As shown in Figure 7-1, each input pin has ESD protection diodes to AVDD and GND. On power-up or after device reset, all eight channels of the multiplexer are configured as analog inputs.

Figure 7-1 Analog Inputs, GPIOs, and ADC Connections

Figure 7-1 shows an equivalent circuit for the pins configured as analog inputs. The ADC sampling switch is represented by an ideal switch (SW) in series with a resistor (R_SW, typically 150 Ω) and a sampling capacitor (C_SH, typically 30 pF). During acquisition, the SW switch is closed to allow the signal on the selected analog input channel to charge the internal sampling capacitor. During conversion, the SW switch is opened to disconnect the analog input channel from the sampling capacitor.

The multiplexer channels can be configured as GPIOs in the PIN_CFG register. On power-up, all channels of the multiplexer are configured as analog inputs. The direction of a GPIO, input or output, can be set in the GPIO_CFG register. The logic level of channels configured as digital inputs can be read from the GPI_VALUE register. The digital outputs can be accessed by writing to the GPO_VALUE register. The digital outputs can be configured as open-drain or push-pull in the GPO_DRIVE_CFG register.