To enable write access to the configuration registers for diagnostics, write 0x96 in the DIAGNOSTICS_KEY register. To enable bit-walk test mode, configure BITWALK_EN = 1b. In the bit-walk test mode (see Figure 6-1), the sampling switch (SW) remains open and the test voltage is applied on the sampling capacitor (C_SH) during the acquisition phase of the ADC. In diagnostic mode, the conversion process of the ADC remains the same as normal device operation. The ADC starts the conversion phase on the rising edge of CS and outputs the code corresponding to the sampled test voltage. The output code of the ADC is expected to be proportional to the test voltage, as shown in Equation 2, after adjusting for DC errors (such as INL, gain error, offset error, and thermal drift of offset and gain errors).

Equation 2.

where

• TUE = Total unadjusted error, given by the root sum square of the offset error, gain error, and INL

The test voltage is generated by a DAC configured by the BIT_SAMPLE_MSB and BIT_SAMPLE_LSB registers. Because the test voltage is derived from the ADC reference, as given by Equation 3, this diagnostic mode is not sensitive to variations in reference voltage.

Equation 3.

To resume conversion of the ADC input signal, configure BITWALK_EN = 0b.