The cyclic redundancy check (CRC) is an error checking code that detects communication errors to and from the host. CRC is the division remainder of the data payload bytes by a fixed polynomial. The data payload is two or three bytes, depending on the output data format; see the Output Data Format section for details on output data format. The CRC mode is optional and is enabled by the CRC_EN bit in the GENERAL_CFG register.

The CRC data byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the argument by a CRC polynomial. The CRC polynomial is based on the CRC-8-CCITT: X⁸ + X² + X¹ + 1. The nine binary polynomial coefficients are: 100000111. The CRC calculation is preset with 1 data values. For more details about the CRC implementation and for a software example, see the Implementation of CRC for ADS7066 application report.

The host must compute and append the appropriate CRC to the command string in the same SPI frame (see the Register Read/Write Operation section). The ADC also computes the expected CRC corresponding to the payload received from the host and compares the calculated CRC code to the CRC received from the host. The CRC received from the host and the CRC calculated by the ADC over the received payload are compared to check for an exact match.

• If the calculated CRC and received CRC match then the data payload received from the host is valid.
• If the calculated CRC and received CRC do not match then the data payload received from the host is not valid and the command does not execute. The CRCERR_IN flag is set to 1b. ADC conversion data read and register read processes, with a valid CRC from the host, are still supported. The error condition can be detected, as listed in Table 6-2, by either status flags or by a register read. Further register writes to the device are blocked until the CRCERR_IN flag is cleared to 0b. Register write operations, with a valid CRC from the host, to the SYSTEM_STATUS (address = 0x00) and GENERAL_CFG (address = 0x01) registers are still supported.

For a conversion data read or register data read, the ADC responds with a CRC that is computed over the requested data payload bytes. The response data payload is one, two, or three bytes depending on the data operation (see the Output CRC (Device to Host) section).