The write operation to the data buffer starts and stops as per the settings in the DATA_BUFFER_OPMODE register. The DATA_BUFFER_STATUS register provides the number of entries filled in the data buffer and this register can be read during an active sequence to get the current status of the data buffer.

The time between two consecutive conversions is set by the NCLK_SEL register and Equation 3 provides the relationship for time between two consecutive conversions of the same channel and nCLK parameter.

where:

• t_cc = Time between two consecutive conversions of the same channel, t_cc = k × t_cycle
• k = Number of channels enabled in the device sequence
• nCLK = Number of clocks used by the device for one conversion cycle
• Oscillator timer period = t_LPO or t_HSO depending on the OSC_SEL value; see the Section 6 section for t_LPO or t_HSO

The format of the 16-bit contents of each entry in the data buffer are set by programming the DOUT_FORMAT_CFG register. The DATA_OUT_CFG register enables the channel ID and DATA_VALID flag in the data buffer. The channel ID represents the channel number for the data entry in the data buffer. DATA_VALID is set to zero in either of the following conditions:

• If the entry in the data buffer is not filled after the last start of the sequence
• If the I²C controller tries to read more than 16 entries from the data buffer, the device provides zeros with DATA_VALID set to zero

At the end of the write operation, the data buffer always has results of 16 (or less) consecutive conversions. The data buffer is filled in the order that the data are converted by the ADC. The channels converted by the ADC are controlled by the AUTO_SEQ_CHEN register. The entries that are not filled during an active sequence are filled with zeros.