ZHCSCB7A January   2014  – April 2014 ADS7251 , ADS7851

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Terminal Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS7251
    6. 6.6  Electrical Characteristics: ADS7851
    7. 6.7  Electrical Characteristics: Common
    8. 6.8  ADS7251 Timing Characteristics
    9. 6.9  ADS7851 Timing Characteristics
    10. 6.10 Typical Characteristics: ADS7251
    11. 6.11 Typical Characteristics: ADS7851
    12. 6.12 Typical Characteristics: Common
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Input
        1. 7.3.2.1 Analog Input Full-Scale Range
        2. 7.3.2.2 Common-Mode Voltage Range
      3. 7.3.3 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
      2. 7.4.2 Short-Cycling Feature
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Amplifier Selection
        2. 8.2.2.2 Antialiasing Filter
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 相关链接
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage AVDD to GND –0.3 +7 V
DVDD to GND –0.3 +7 V
Analog input voltage AINP_x to REFGND_x REFGND_x – 0.3 AVDD + 0.3 V
AINM_x to REFGND_x REFGND_x – 0.3 AVDD + 0.3 V
Digital input voltage CS, SCLK to GND GND – 0.3 DVDD + 0.3 V
Ground voltage difference | REFGND_x – GND | 0.3 V
Input current Any pin except supply pins ±10 mA
Maximum virtual junction temperature, TJ +150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 +150 °C
VESD(1),
all pins		 Human body model (HBM) ESD stress voltage(2),
JEDEC standard 22, test method A114-C.01		 ±2000 V
Charged device model (CDM) ESD stress voltage(3),
JEDEC standard 22, test method C101		 ±500 V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that ±2000-V HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that ±500-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage 5 V
DVDD Digital supply voltage 3.3 V

6.4 Thermal Information

THERMAL METRIC(1) ADS7251, ADS7851 UNIT
RTE (WQFN)
16 TERMINALS
RθJA Junction-to-ambient thermal resistance 33.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.5
RθJB Junction-to-board thermal resistance 7.3
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 7.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: ADS7251

All minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 5 V, VREF_A = VREF_B = 2.5 V, and fDATA =
2 MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 12 Bits
SAMPLING DYNAMICS
tCONV Conversion time tSU_CSCK + 12 tCLK ns
tACQ Acquisition time 75 ns
fDATA Data rate 2 MSPS
fCLK Clock frequency 32 MHz
DC ACCURACY
NMC No missing codes 12 Bits
DNL Differential nonlinearity –0.99 ±0.3 1 LSB
INL Integral nonlinearity –1 ±0.5 1 LSB
VOS Input offset error –1 ±0.2 1 mV
VOS match ADC_A to ADC_B –1 ±0.2 1 mV
dVOS/dT Input offset thermal drift 4 μV/°C
GE Gain error Referenced to the voltage at REFOUT_x –0.1% ±0.05% 0.1%
GERR match ADC_A to ADC_B –0.1% ±0.05% 0.1%
GE/dT Gain error thermal drift Referenced to the voltage at REFOUT_x 1 ppm/°C
CMRR Common-mode rejection ratio Both ADCs, dc to 20 kHz 72 dB
AC ACCURACY
SINAD Signal-to-noise + distortion For 20-kHz input frequency,
at –0.5 dBFS		 72.7 72.9 dB
SNR Signal-to-noise ratio 72.8 73 dB
THD Total harmonic distortion –90 dB
SFDR Spurious-free dynamic range 90 dB
Isolation between ADC_A and ADC_B fIN = 15 kHz, fNOISE = 25 kHz –105 dB
SUPPLY CURRENT
IAVDD-DYNAMIC Supply current Analog, during conversion Throughput = 2 MSPS,
AVDD = 5 V		 11 12 mA
IAVDD-STATIC Analog, static 5.5 mA
IDVDD Digital, for code 800 0.15 mA
POWER DISSIPATION
PD-ACTIVE Power dissipation During conversion Throughput = 2 MSPS,
AVDD = 5 V		 55 60 mW
PD-STATIC Static mode 27.5 mW

6.6 Electrical Characteristics: ADS7851

All minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 5 V, VREF_A = VREF_B = 2.5 V, and fDATA =
1.5 MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 14 Bits
SAMPLING DYNAMICS
tCONV Conversion time tSU_CSCK + 14 tCLK ns
tACQ Acquisition time 90 ns
fDATA Data rate 1500 kSPS
fCLK Clock frequency 27 MHz
DC ACCURACY
NMC No missing codes 13 Bits
DNL Differential nonlinearity –1 ±0.75 2 LSB
INL Integral nonlinearity –2 ±1 2 LSB
VOS Input offset error –1 ±0.2 1 mV
VOS match ADC_A to ADC_B –1 ±0.2 1 mV
dVOS/dT Input offset thermal drift 1 μV/°C
GE Gain error Referenced to the voltage at REFOUT_x –0.1% ±0.05% 0.1%
GERR match ADC_A to ADC_B –0.1% ±0.05% 0.1%
GE/dT Gain error thermal drift Referenced to the voltage at REFOUT_x 1 ppm/°C
CMRR Common-mode rejection ratio Both ADCs, dc to 20 kHz 72 dB
AC ACCURACY
SINAD Signal-to-noise + distortion For 20-kHz input frequency,
at –0.5 dBFS		 81.4 82.6 dB
SNR Signal-to-noise ratio 82 83.5 dB
THD Total harmonic distortion –90 dB
SFDR Spurious-free dynamic range 90 dB
Isolation between ADC_A and ADC_B fIN = 15 kHz, fNOISE = 25 kHz –120 dB
SUPPLY CURRENT
IAVDD-DYNAMIC Supply current Analog, during conversion Throughput = 1.5 MSPS,
AVDD = 5 V		 10 12 mA
IAVDD-STATIC Analog, static 5.5 mA
IDVDD Digital, for code 2000 0.15 mA
POWER DISSIPATION
PD-ACTIVE Power dissipation During conversion Throughput = 1.5 MSPS,
AVDD = 5 V		 50 60 mW
PD-STATIC Static mode 27.5 mW

6.7 Electrical Characteristics: Common

All minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 5 V, VREF_A = VREF_B = 2.5 V, and fDATA =
2 MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR Full-scale input range
(AINP_x – AINM_x)		 For AVDD ≥ 5 V –2 VREF 2 VREF V
For AVDD < 5 V –AVDD AVDD V
VIN Absolute input voltage
(AINP_x or AIM_x to REFGND_x)		 For AVDD ≥ 5 V 0 2 VREF V
For AVDD < 5 V 0 AVDD V
VCM Input common-mode voltage range VREF_A = VREF_B = VREF VREF – 0.1 VREF VREF + 0.1 V
CIN Input capacitance In sample mode 40 pF
In hold mode 4 pF
SAMPLING DYNAMICS
tA Aperture delay 8 ns
tA match ADC_A to ADC_B 40 ps
BW Full-power bandwidth At 3 dB 25 MHz
At 0.1 dB 5 MHz
INTERNAL VOLTAGE REFERENCE
VREFOUT Internal reference output voltage At +25°C 2.495 2.500 2.505 V
VREFOUT-match VREFOUT matching | REFOUT_A – REFOUT_B | ±1 mV
dVREFOUT/dt Long-term voltage drift 1000 hours 150 ppm
dVREFOUT/dT Reference voltage drift with temperature ±10 ppm/°C
RO Internal reference output impedance 1 Ω
COUT External output capacitor 22 μF
Internal reference output settling time COUT = 22 μF 10 ms
DIGITAL INPUTS(1)
VIH Input voltage, high 0.7 DVDD DVDD + 0.3 V
VIL Input voltage, low –0.3 0.3 DVDD V
CIN Input capacitance 5 pF
IIN Input leakage current 0 ≤ Vdigital-input ≤ DVDD ±0.1 1 μA
DIGITAL OUTPUTS(1)
VOH Output voltage, high IOH = 500-µA source 0.8 DVDD DVDD V
VOL Output voltage, low IOH = 500-µA sink 0 0.2 DVDD V
POWER SUPPLY
AVDD Supply voltage Analog (AVDD to GND) 4.75(2) 5.0 5.25 V
DVDD Digital (DVDD to GND) Operational range 1.65 3.3 5.25 V
For specified performance 1.65 3 3.6 V
TEMPERATURE RANGE
TA Operating free-air temperature –40 +125 °C
(1) Specified by design; not production tested.
(2) The AVDD supply voltage defines the permissible voltage swing on the analog input pins. Refer to the Power Supply Recommendations section for more details.

6.8 ADS7251 Timing Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fTHROUGHPUT Throughput fCLK = max 2000 kSPS
fCLK CLOCK frequency fTHROUGHPUT = max 32 MHz
tCLK CLOCK period fTHROUGHPUT = max 31.25 ns
tPH_CK CLOCK high time 0.45 0.55 tCLK
tPL_CK CLOCK low time 0.45 0.55 tCLK
tCONV Conversion time tSU_CSCK + 12 tCLK ns
tACQ Acquisition time fCLK = max 75 ns
tPH_CS CS high time 30 ns
tD_CKDO Delay time SCLK rising edge to (next) data valid 15 ns
tDV_CSDO CS falling to data enable 10 ns
tD_CKCS Last SCLK rising to CS rising 5 ns
tDZ_CSDO CS rising to DOUT going to 3-state 10 ns
tSU_CSCK Setup time CS falling to SCLK falling 15 ns

Figure 1 shows the details of the serial interface between the ADS7251 and the digital host controller.

tim_ADS7251_bas587.gifFigure 1. ADS7251 Serial Interface Timing Diagram

6.9 ADS7851 Timing Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fTHROUGHPUT Sample taken to data read fCLK = max 1500 kSPS
fCLK CLOCK frequency fTHROUGHPUT = max 27 MHz
tCLK CLOCK period fTHROUGHPUT = max 37 ns
tPH_CK CLOCK high time 0.45 0.55 tCLK
tPL_CK CLOCK low time 0.45 0.55 tCLK
tCONV Conversion time tSU_CSCK + 14 tCLK ns
tACQ Acquisition time fCLK = max 90 ns
tPH_CS CS high time 30 ns
tD_CKDO Delay time SCLK rising edge to (next) data valid 15 ns
tDV_CSDO CS falling to data enable 10 ns
tD_CKCS Last SCLK rising to CS rising 5 ns
tDZ_CSDO CS rising to DOUT going to 3-state 10 ns
tSU_CSCK Setup time CS falling to SCLK falling 15 ns

Figure 2 shows the details of the serial interface between the ADS7851 and the digital host controller.

tim_ADS7851_bas587.gifFigure 2. ADS7851 Serial Interface Timing Diagram

6.10 Typical Characteristics: ADS7251

At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
C002_SBAS587.png
fIN = 500 kHz
Figure 3. Typical FFT for 500-kHz Input
C004_SBAS587.png
fIN = 10 kHz
Figure 5. SINAD vs Device Temperature
C005_SBAS587.png
fIN = 10 kHz
Figure 7. SNR vs Input Frequency
C009_SBAS587.png
Figure 9. THD vs Input Frequency
C016_SBAS587.png
Figure 11. Typical DNL
C018_SBAS587.png
Figure 13. DNL vs Device Temperature
C014_SBAS587.png
Figure 15. Offset Error vs Device Temperature
C020_SBAS587.png
Figure 17. IAVDD vs Device Temperature
C003_SBAS587.png
fIN = 10 kHz
Figure 4. SNR vs Device Temperature
C007_SBAS587.png
fIN = 10 kHz
Figure 6. THD vs Device Temperature
C006_SBAS587.png
Figure 8. SINAD vs Input Frequency
C011_SBAS587.png
VIN-DIFF = 0 V 65536 Data Points
Figure 10. DC Histogram
C017_SBAS587.png
Figure 12. Typical INL
C019_SBAS587.png
Figure 14. INL vs Device Temperature
C015_SBAS587.png
Figure 16. Gain Error vs Device Temperature
C021_SBAS587.png
Figure 18. IAVDD vs Throughput

6.11 Typical Characteristics: ADS7851

At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
C023_SBAS587.png
fIN = 500 kHz
Figure 19. Typical FFT for 500-kHz Input
C025_SBAS587.png
fIN = 10 kHz
Figure 21. SINAD vs Device Temperature
C026_SBAS587.png
fIN = 10 kHz
Figure 23. SNR vs Input Frequency
C030_SBAS587.png
Figure 25. THD vs Input Frequency
C037_SBAS587.png
Figure 27. Typical DNL
C039_SBAS587.png
Figure 29. DNL vs Device Temperature
C035_SBAS587.png
Figure 31. Offset Error vs Device Temperature
C041_SBAS587.png
Figure 33. IAVDD vs Device Temperature
C024_SBAS587.png
fIN = 10 kHz
Figure 20. SNR vs Device Temperature
C028_SBAS587.png
fIN = 10 kHz
Figure 22. THD vs Device Temperature
C027_SBAS587.png
Figure 24. SINAD vs Input Frequency
C032_SBAS587.png
VIN-DIFF = 0 V 65536 Data Points
Figure 26. DC Histogram
C038_SBAS587.png
Figure 28. Typical INL
C040_SBAS587.png
Figure 30. INL vs Device Temperature
C036_SBAS587.png
Figure 32. Gain Error vs Device Temperature
C042_SBAS587.png
Figure 34. IAVDD vs Throughput

6.12 Typical Characteristics: Common

At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, and VREF = 2.5 V (internal), unless otherwise noted.
C033_SBAS587.png
Figure 35. Reference Output vs
Device Temperature
C043_SBAS587.png
Figure 37. CMRR vs Input Frequency
C034_SBAS587.png
Rout = 0.75 Ω Typ
Figure 36. Internal Reference:
Output Current vs Output Voltage
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