米6体育平台手机版

ZHCSK88A September 2010 – September 2019 ADS7947 , ADS7948 , ADS7949

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RTE|16
- MPQF149D

散热焊盘机械数据 (封装 | 引脚)

RTE|16
- QFND525B

订购信息

7.6 Electrical Characteristics: ADS7948 (10-Bit)

minimum and maximum values at AVDD = 2.7 V to 5.5 V, DVDD = 1.65 V to AVDD, T_A = –40°C to +125°C, and
f_SAMPLE = 2 MSPS (unless otherwise noted); typical values at AVDD = 3 V, DVDD = 1.8 V, T_A = +25°C, and f_SAMPLE = 2 MSPS

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
Input capacitance⁽⁴⁾				32		pF
Input leakage current		At +125°C		1.5		nA
SYSTEM PERFORMANCE
Resolution				10		Bits
No missing codes			10			Bits
Integral linearity			–0.5	±0.15	0.5	LSB⁽¹⁾
Differential linearity			–0.5	±0.15	0.5	LSB
Offset error⁽²⁾			–0.5	±0.15	0.5	LSB
Gain error			–0.5	±0.15	0.5	LSB
Transition noise					25	µV_RMS
Power-supply rejection				60		dB
SAMPLING DYNAMICS
Conversion time					10.5	SCLK
Acquisition time			80			ns
Maximum sample rate (throughput rate)		34-MHz SCLK in 16-clock frame			2	MSPS
Maximum sample rate (throughput rate)		34-MHz SCLK and CS low for 10.5 clocks			2.57	MSPS
Aperture delay					5	ns
Aperture jitter				10		ps
Step response				80		ns
Overvoltage recovery				80		ns
DYNAMIC CHARACTERISTICS
Total harmonic distortion (THD)⁽³⁾		100kHz		–80		dB
Signal-to-noise ratio (SNR)		100 kHz	61			dB
Signal-to-noise and distortion ratio (SINAD)		100 kHz		61		dB
Spurious-free dynamic range (SFDR)		100 kHz		81		dB
Full-power bandwidth		At –3 dB		15		MHz
DIGITAL INPUT/OUTPUT
Logic family		CMOS
Logic level	V_IH		0.7DVDD			V
	V_IL			0.3DVDD		V
	V_OH	I_SOURCE = 200 µA	DVDD – 0.2			V
	V_OL	I_SINK = 200 µA	0.4			V
Input leakage current	I_IH, I_IL	0 < V_IN < DVDD		±20		nA
POWER-SUPPLY REQUIREMENTS
AVDD supply current	I_DYNAMIC	AVDD = 3.3 V, f_SAMPLE = 2 MSPS		2.5		mA
	I_DYNAMIC	AVDD = 5 V, f_SAMPLE = 2 MSPS		3	3.5	mA
	I_STATIC	AVDD = 3.3 V, SCLK off		1.8		mA
	I_STATIC	AVDD = 5 V, SCLK off		1.9	2.5	mA
DVDD supply current⁽⁵⁾		DVDD = 3.3 V, SCLK = 34 MHz, SDO load 20 pF		500		µA
Power-down state AVDD supply current	I_PD-DYNAMIC	SCLK = 34 MHz			550	µA
Power-down state AVDD supply current	I_PD-STATIC	SCLK off			2.5	µA
Power-up time					1	µs

(1) LSB means least significant bit.

(2) Measured relative to an ideal full-scale input.

(3) Calculated on the first nine harmonics of the input frequency.

(4) See Figure 40 for sampling circuit details.

(5) DVDD consumes only dynamic current. I_DVDD = C_LOAD × DVDD × number of 0→1 transitions in SDO × f_SAMPLE. This current is load-dependent and there is no DVDD current when the output is not toggling.