8.3.3 Clock

The ADS794x use SCLK for conversions (typically 34 MHz). A lower frequency SCLK can be used for applications requiring sample rates less than 2 MSPS. However, using a 34-MHz SCLK and slowing down the device speed by choosing a lower frequency for CS is better, which allows more acquisition time. This configuration relaxes constraints on the output impedance of the driving circuit. See the Application Information section for a calculation of the driving circuit output impedance.