米6体育平台手机版

ZHCSK88A September 2010 – September 2019 ADS7947 , ADS7948 , ADS7949

PRODUCTION DATA.

at DVDD⁽¹⁾ = 1.65 V to AVDD (unless otherwise noted); minimum and maximum values at T_A = –40°C to +125°C, typical values at T_A = 25°C

			MIN	NOM	MAX	UNIT
CONVERSION CYCLE
f_SAMPLE	Sample rate (throughput rate)	SCLK = 34 MHz, 16 clock frame			2	MSPS
	f_{SAMPLE MAX} = 1 / ( t_{CONV MAX} + t_{ACQ MIN})	ADS7947 (12 bit), SCLK = 34 MHz			2.1	MSPS
		ADS7948 (10 bit), SCLK = 34 MHz			2.57
		ADS7949 (8 bit), SCLK = 34 MHz			3
t_ACQ	Acquisition time		80			ns
POWER DOWN
t_PDSU	Setup time, PDEN high to CS rising edge (see Figure 45 and Figure 46)		2			ns
t_PDH	Hold time, CS rising edge to PDEN falling edge (see Figure 45)		20			ns
SPI INTERFACE TIMINGS
t_W1	Pulse duration, CS high		25			ns
t_SU1	Setup time, CS low to first rising edge of SCLK	DVDD = 1.8 V	3.5			ns
		DVDD = 3 V	3.5
		DVDD = 5 V	3.5
t_D4	Delay time, CS rising edge from conversion end (see the t_CONV specification for conversion time)		10			ns
t_WH	Pulse duration, SCLK high		11			ns
t_WL	Pulse duration, SCLK low		11			ns
f_SCLK	SCLK frequency		0.4	34	40	MHz

(1) 1.8-V specifications apply from 1.65 V to 2 V; 3-V specifications apply form 2.7 V to 3.6 V; 5-V specifications apply from 4.75 V to 5.25 V.