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ZHCSIK6D November 2017 – June 2024 ADS8166 , ADS8167 , ADS8168

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RHB|32
- MPQF130D

散热焊盘机械数据 (封装 | 引脚)

RHB|32
- QFND029X

订购信息

6.5.1.1.1 Protocols for Configuring the Device

As described in Table 6-6, the host controller uses any of the four SPI protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to write data into the device.

Table 6-6 SPI Protocols for Configuring the Device

PROTOCOL	SCLK POLARITY (At the CS Falling Edge)	SCLK PHASE (Capture Edge)	SDI_MODE[1:0] BITS⁽¹⁾	SDO_MODE[1:0] BITS⁽²⁾	DIAGRAM
SPI-00	Low	Rising	00h	00h	Figure 6-19
SPI-01	Low	Falling	01h	00h	Figure 6-19
SPI-10	High	Falling	02h	00h	Figure 6-20
SPI-11	High	Rising	03h	00h	Figure 6-20

(1) See the SDI_CNTL register.

(2) See the SDO_CNTL1 register.

On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data read and data write operations. To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits in the SDI_CNTL register. Make sure this first write operation adheres to the SPI-00-S protocol. Make sure any subsequent data transfer frames adhere to the newly selected protocol. The SPI protocol selected by the SDI_MODE[1:0] configuration is applicable to both read and write operations.

Figure 6-19 and Figure 6-20 detail the four protocols using an optimal data frame.

ADS8166 ADS8167 ADS8168 Standard
SPI Timing Protocol (CPHA = 0)

Figure 6-19 Standard SPI Timing Protocol (CPHA = 0)

ADS8166 ADS8167 ADS8168 Standard
SPI Timing Protocol (CPHA = 1)

Figure 6-20 Standard SPI Timing Protocol (CPHA = 1)

Note:

As explained in the Register Read/Write Operation section, a valid register read or write operation to the device requires 24 SCLKs to be provided within a data transfer frame. When reading ADC conversion data, a minimum 16 SCLKs are required within a data transfer frame.