9.3.2.1 Driver Amplifier Choice

To take advantage of the high sample rate offered by the ADS833x, the analog inputs to the converter should be driven with low-noise operational amplifiers (op amps), such as the OPA365, OPA211, OPA827, or THS4031. TI recommends a RC filter at each of the input channels to low-pass filter noise generated by the input driving sources. These channels can accept unipolar signals with voltages between IN_X and COM in the range of 0 V to V_REF. If RC filters are not used between the op amps and the input channels, the minimum –3-dB bandwidth required by the driving op amps for the sampled signals to settle to within 1/2 LSB of the final voltage can be calculated using Equation 1:

Equation 1.

where

• n = resolution of the converter (n = 16 for the ADS833x).
• t_{SAMPLE_MIN} = minimum acquisition time.

The minimum value of t_SAMPLE in Electrical Characteristics: VA = 2.7 V and Electrical Characteristics: VA = 5 V is 238 ns (3 CCLKs with the internal oscillator at 12.6 MHz). Substituting these values for n and t_{SAMPLE_MIN} into Equation 1 shows f_{–3 dB} must be at least 7.9 MHz. This bandwidth can be relaxed if the acquisition time is increased or an RC filter is added between the driving operational amplifier and the corresponding input channel (see Texas Instruments' Application Report, Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to the Input (SBAA173) and associated references for additional information, available for download at www.ti.com). The OPA365 used in the source-follower (unity-gain) configuration is shown in Figure 35 with recommended values for the RC filter.

Figure 35. Unipolar Input Drive Configuration

9.3.2.2 Bipolar to Unipolar Driver

In systems where the input signal is bipolar, op amps such as the OPA365 and OPA211 can be used in the inverting configuration with a DC bias applied to the noninverting input to keep the input signal to the ADS833x within its rated operating voltage range. TI also recommends this configuration when the ADS833x is used in signal-processing applications where good SNR and THD performance is required. The DC bias can be derived from low-noise reference voltage ICs such as the REF5025 or REF5040. The input configuration shown in Figure 36 is capable of delivering better than 91-dB SNR and –99-dB THD at an input frequency of 1 kHz. If bandpass filters are used to filter the input to the driving operational amplifier, the signal swing at the input of the bandpass filter should be small enough to minimize the distortion introduced by the filter. In these cases, the gain of the circuit shown in Figure 36 can be increased to maintain a large enough input signal to the ADS833x to keep the system SNR as high as possible.

Figure 36. Bipolar Input Drive Configuration

9.4.2.1 Manual Channel Select Mode

Manual Channel Select mode is enabled through the Configuration register (CFR) by setting the CFR_D11 bit to 0 (see Table 5). The acquisition process starts with selecting an input channel. This selection is done by writing the desired channel number to the Command register (CMR); see Table 4 for further details. The associated timing diagram is shown in Figure 38.

Figure 38. Manual Channel Select Timing

9.4.2.2 Auto Channel Select Mode

Channel selection can also be done automatically if Auto Channel Select mode (default) is enabled (CFR_D11 = 1). If the device is programmed for Auto Channel Select mode, then signals from all channels are acquired in a fixed order. In Auto Channel Select mode, the first conversion after entering this mode is always from the channel of the last conversion completed before this mode is enabled. The channels are then sequentially scanned up to and including the last channel (that is, channel 3 for the ADS8331 and channel 7 for the ADS8332) and then back to the channel that started the sequence. For example, if the last channel used in the conversion before enabling Auto Channel Select mode was channel 2, the sequence for the ADS8332 would be: 2, 3, 4, 5, 6, 7, 2, and so forth, as shown in Figure 39. If the last channel in Manual Channel Select mode happened to be channel 7, the sequence would be: 7, 7, 7, and so forth. Figure 40 shows when the next channel in the sequence activates during Auto Channel Select mode. This timing allows the next channel to settle before it is acquired. This automatic sequencing stops the cycle after CFR_D11 is set to 0.

Figure 39. Auto Channel Select for the ADS8332

Figure 40. Channel-Number Update in Auto Channel Select Mode Timing

9.4.2.3 Start of a Conversion

The end of acquisition is the same as the start of a conversion. This process is initiated by bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that require simultaneous sample/hold with multiple converters. The ADS833x switches from sample to hold mode on the falling edge of the CONVST signal. The ADS833x requires 18 conversion clock (CCLK) cycles to complete a conversion. The conversion time is equivalent to 1500 ns with a 12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs.

A conversion can also be initiated without using CONVST if the ADS833x is programmed for Auto-Trigger mode (CFR_D9 = 0). When the converter is configured in this mode, and with CFR_D8 = 0, the next conversion is automatically started three conversion clocks (CCLK) after the end of a conversion. These three conversion clocks (CCLK) are used for the acquisition time. In this case, the time to complete one acquisition and conversion cycle is 21 CCLKs. Table 1 summarizes the different conversion modes.

Manual Channel select with Auto-Trigger mode enabled is generally used when continuous conversions from a single channel are desired. In this mode, cycling the input mux to change the channel requires that conversions are halted by setting the converter to Manual-Trigger mode. When the proper input channel is selected, the converter can be placed back to Auto-Trigger mode to continue continuous conversions from the new channel.

9.4.2.4 Status Output Pin (EOC/INT)

The status output pin is programmable. It can be used as an EOC output (CFR_D[7:6] = 11) where the low time is equal to the conversion time. When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following manner: the EOC output goes low immediately following CONVST going low with Manual-Trigger mode enabled. EOC stays low throughout the conversion process and returns high when the conversion has ended. If Auto-Trigger mode is enabled, the EOC output remains high for three conversion clocks (CCLK) after the previous rising edge of EOC.

This status pin can also be used as an interrupt output, INT (CFR_D[7:6] = 10), which is set low at the end of a conversion, and is brought high (cleared) by the next read cycle. The polarity of this pin, whether used as EOC or INT, is programmable through the CFR_D7 bit.

9.4.2.5 Power-Down Modes and Acquisition Time

There are three power-down modes that reduce power dissipation: Nap, Deep, and Auto-NAP. The first two, Nap and Deep Power-Down modes, are enabled or disabled by bits CFR_D3 and CFR_D2, respectively, in the Configuration register (see Table 5 for details).

Deep Power-Down mode provides maximum power savings. When this mode is enabled, the analog core in the converter is shut down, and the analog supply current falls from 6.6 mA (VA = 5 V) to 1 μA in 2 μs. The wake-up time from Deep Power-Down mode is 1 μs. The device can wake up from Deep Power-Down mode by either disabling this mode, issuing the wake-up command, loading the default value into the CFR, or performing a reset (either with the software reset command, CFR_D0 bit, or the external reset). See Table 4 and Table 5 along with the section for further information.

In Nap Power-Down mode, the bias currents for the analog core of the device are significantly reduced. Because the bias currents are not completely shut off, the ADS833x can wake up from this power-down mode much faster than from Deep Power-Down mode. After Nap Power-Down mode is enabled, the analog supply current falls from 6.6 mA (VA = 5 V) to 0.39 mA in 200 ns. The wake-up time from this mode is three conversion clock cycles (CCLK). The device can wake up from Nap Power-Down mode in the same manner as waking up from Deep Power-Down mode.

The third power-down mode, Auto-NAP, is enabled or disabled by bit CFR_D4 in the Configuration register (see Table 5 for details). Once this mode is enabled, the device is controlled by the digital core logic on the chip. The device is automatically placed into Nap Power-Down mode after the next end of conversion (EOC). The analog supply current falls from 6.6mA (VA = 5 V) to 0.39 mA in 200 ns. A conversion start wakes up the device in three conversion clock cycles. Issuing the wake-up command, loading the default value into the CFR, disabling Auto-NAP Power-Down mode, issuing a manual channel select command, or resetting the device can wake the ADS833x from Auto-NAP Power-Down mode. A comparison of the three power-down modes is listed in Table 2.

The default acquisition time is three conversion clock (CCLK) cycles. Figure 41 shows the timing diagram for CONVST, EOC, and Auto-NAP power-down signals in Manual-Trigger mode. As shown in the diagram, the device wakes up after a conversion is triggered by the CONVST pin going low. However, a conversion is not yet started at this time. The conversion start signal to the analog core of the chip is internally generated no less than six conversion clock (CCLK) cycles later, to allow at least three CCLKs for wake up and three CCLKs for acquisition. The ADS833x enters Nap Power-Down mode one conversion cycle after the end of conversion (EOC).

Figure 41. Timing for CONVST, EOC, and Auto-NAP Power-Down Signals in Manual-Trigger Mode (Three Conversion Clock Cycles for Acquisition)

The ADS833x can support sampling rates of up to 500 kSPS in Auto-Trigger mode. This rate is selectable by programming the CFR_D8 bit in the Configuration register. In 500-kSPS mode, consecutive conversion start pulses to the analog core are generated 21 conversion clock cycles apart. In 250-kSPS mode, consecutive conversion-start pulses are 42 conversion clock cycles apart. The Nap and Deep Power-Down modes are available with either sampling rate; however, Auto-NAP mode is available only with a sampling rate of 250 kSPS when Auto-Trigger mode is enabled. The analog core cannot be powered down when the Auto-NAP mode sampling rate is 500 kSPS because at that rate, there is no period of time when the analog core is not actively being used.

Figure 42 shows the timing diagram for conversion start and Auto-NAP power-down signals for a 250-kSPS sampling rate in Auto-Trigger mode. For a 16-bit ADC output word, consecutive new conversion start pulses are generated 2 × (18 + 3) cycles apart. NAP_ACTIVE (the signal to power down the analog core in Nap and Auto-NAP modes) goes low six (3 + 3) conversion clock cycles before the conversion start falling edge, thus powering up the analog core. It takes three conversion clock cycles after NAP_ACTIVE goes low to power up the analog core. The analog core is powered down a cycle after the end of a conversion. For a 16-bit ADC with a 500-kSPS sampling rate and three conversion clock cycle sampling, consecutive conversion start pulses are generated 21 conversion clock cycles apart.

Figure 42. Timing for Conversion Start and Auto-NAP Power-Down Signals in Auto-Trigger Mode (250-kSPS Sampling and Three Conversion Clock Cycles for Acquisition)

Timing diagrams for reading from the ADS833x with various trigger and power-down modes are shown in Figure 43 through Figure 45. The total (acquisition + conversion) times for the different trigger and power-down modes are listed in Table 3.

Figure 43. Read While Converting vs Read While Sampling (Manual-Trigger Mode)

BLANKSPACE

1. Converter is in acquisition mode between end of conversion and activation of Nap or Deep Power-Down mode.

2. Command on SDI pin to wake-up converter (minimum of four SCLKs).

3. Command on SDI pin to place converter into Nap or Deep Power-Down mode (minimum of 16 SCLKs).

Figure 44. Read While Converting vs Read While Sampling With Nap or Deep Power Down
(Manual-Trigger Mode)

1. Time between end of conversion and Nap Power Down mode is 1 CCLK.

2. Command on SDI to wake-up converter (minimum of four SCLKs).

Figure 45. Read While Converting vs Read While Sampling With Auto-NAP Power Down

9.5.1.1 Internal Register

The internal register consists of two parts: four bits for the Command register (CMR) and 12 bits for the Configuration register (CFR).

9.5.2.1 Configuring the Converter and Default Mode

The converter can be configured with command 1110b (write to the CFR) or command 1111b (default mode). A write to the CFR requires a 4-bit command followed by 12 bits of data. A 4-bit command takes effect on the fourth falling edge of SCLK. A write to the CFR takes effect on the 16th falling edge of SCLK.

The CFR default value for each bit is 1. The default values are applied to the CFR after issuing command 1111b or when the device is reset with a power-on reset (POR), software reset, or external reset using the RESET pin (see the Reset Function section).

The communication protocol of the ADS833x is full duplex. That is, data are transmitted to and from the device simultaneously. For example, the input mux channel can be changed via the SDI pin while data are being read through the SDO pin. All commands, except Read CFR, output conversion data on the SDO pin. If a Read CFR command is issued, the Read Data command can then be used to read back the conversion result.

Table 5. Configuration Register (CFR) Map

Table 6. Ideal Input Voltages and Output Codes

9.5.4.1 TAG Mode

The ADS833x includes a TAG feature that can be used to indicate which channel sourced the converted result. If TAG mode is enabled, three address bits are added after the LSB of the conversion data is read out from SDO to indicate which channel corresponds to the result. These address bits are 000 for channel 0, 001 for channel 1, 010 for channel 2, 011 for channel 3, 100 for channel 4, 101 for channel 5, 110 for channel 6, and 111 for channel 7. The converter requires at least 19 SCLKs when TAG mode is enabled to transfer the 16-bit conversion result and the three TAG bits.

9.5.4.2 Daisy-Chain Mode

The ADS833x can operate as a single converter or in a system with multiple converters. System designers can take advantage of the simple, high-speed, SPI-compatible serial interface by cascading converters in a single chain when multiple converters are used. The CFR_D5 bit in the Configuration register is used to reconfigure the EOC/INT status pin as the chain data input (CDI) pin, a secondary serial data input, for the conversion result from an upstream converter. This configuration is called daisy-chain mode operation. A typical connection of three converters in daisy-chain mode is shown in Figure 46.

Figure 46. Multiple Converters Connected Using Daisy-Chain Mode

When multiple converters are used in daisy-chain mode, the first converter is configured in regular mode while the rest of the converters downstream are configured in daisy-chain mode. When a converter is configured in daisy-chain mode, the CDI input data go straight to the output register. Therefore, the serial input data passes through the converter with either a 16 SCLK (if the TAG feature is disabled) or 24-SCLK delay, as long as CS is active. See Figure 47 for detailed timing. In this timing diagram, the conversion in each converter is performed simultaneously.

Figure 47. Simplified Dasiy-Chain Mode Timing With Shared CONVST and Continuous CS

The multiple CS signals must be handled with care when the converters are operating in daisy-chain mode. The different chip select signals must be low for the entire data transfer (in this example, 48 bits for three conversions). The first 16-bit word after the falling chip select is always the data from the chip that received the chip select signal.

Case 1: If chip select is not toggled (CS stays low), the next 16 bits of data are from the upstream converter, and so on. This configuration is shown in Figure 47.

Case 2: If the chip select is toggled during a daisy-chain mode data transfer cycle, as illustrated in Figure 48, the same data from the converter are read out again and again in all three discrete 16-bit cycles. This state is not a desired result.

Figure 48. Simplified Daisy-Chain Mode Timing With Shared CONVST and Noncontinuous CS

Figure 49 shows a slightly different scenario where CONVST is not shared with the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data downstream.

1. Data from device #2 is from previous converison.

Figure 49. Simplified Daisy-Chain Mode Timing with Separate CONVST and Continuous CS

The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG mode, daisy-chain mode, and the manner in which a channel is selected (for example, Auto Channel Select mode). The required number of SCLKs for different readout modes are listed in Table 7.

SCLK skew between converters in a daisy-chain configuration can affect the maximum frequency of SCLK. The skew can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in daisy-chain mode.