7.4.1 Serial Interface

The devices support a simple, SPI-compatible serial interface to the external digital host. The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The SDO_A and SDO_B pins output the ADC_A and ADC_B conversion results, respectively. Figure 52 shows a detailed timing diagram for these devices.

Figure 52. Serial Interface Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a '0' on the SDO_A and SDO_B pins. The device converts the sampled analog input during the next 14 clocks. SDO_A and SDO_B read '0' during this period. The sample-and-hold circuit goes back into sample mode on the 15th SCLK falling edge and the MSBs of ADC_A and ADC_B are output on SDO_A and SDO_B, respectively. The subsequent clock edges are used to shift out the conversion result using the serial interface, as shown in Table 2. Output data are in binary twos complement format. A CS rising edge ends the frame and puts the serial bus into 3-state.