7.4.2 Short-Cycling, Frame Abort, and Reconversion Feature

Referring to Table 2, the ADS8350 requires a minimum of 31 SCLK falling edges between the beginning and end of the frame to complete the 16-bit data transfer, the ADS7850 requires a minimum of 29 SCLK falling edges between the beginning and end of the frame to complete the 14-bit data transfer, and the ADS7250 requires a minimum of 27 SCLK falling edges between the beginning and end of the frame to complete the 12-bit data transfer. However, CS can be brought high at any time during the frame to abort the frame or to short-cycle the converter.

As shown in Figure 53, if CS is brought high before the 15th SCLK falling edge, the device aborts the conversion and starts sampling the new analog input signal.

Figure 53. Frame Aborted before 15th SCLK Falling Edge

If CS is brought high after the 15th SCLK falling edge (as shown in Figure 54), the output data bits latched into the digital host before this CS rising edge are still valid data corresponding to sample N.

Figure 54. Frame Aborted after 15th SCLK Falling Edge

After aborting the current frame, CS must be kept high for t_{PH_CS_SHRT} to ensure that the minimum acquisition time (t_ACQ) is provided for the next conversion.