ZHCSJ89B January 2019 – July 2022 ADS8353-Q1
PRODUCTION DATA
The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device.
The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. Between the start and end of the frame, a minimum of N SCLK falling edges must be provided to validate the read or write operation. As shown in Table 7-4, N depends upon the interface mode used to read the conversion result. When N SCLK falling edges are provided, the write operation attempted in the frame is validated and the internal user-programmable registers are updated on the subsequent CS rising edge. This CS rising edge also ends the frame.
| INTERFACE MODE | MINIMUM SCLK FALLING EDGES REQUIRED TO VALIDATE WRITE OPERATION N |
|---|---|
| 32-CLK, dual-SDO mode (default); see the Section 7.5.3.2.1 section | 32 |
| 32-CLK, single-SDO mode; see the Section 7.5.3.2.2 section | 48 |
If CS is brought high before providing N SCLK falling edges, the write operation attempted in the frame is not valid. See the Section 7.5.5 section for more details.