In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down. However, the contents of the REFDAC_A and REFDAC_B registers are retained.

As shown in Figure 7-10, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS signal.

To remain in SPD mode, SDI must remain high in all subsequent frames.

Figure 7-10 Enter SPD Mode

As shown in Figure 7-11, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be kept low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising edge following frame (F+3). After frame (F+3), a delay of t_{PU_SPD} must elapse before programming the configuration register.

A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at least 48 SCLK falling edges. Discard the output data in frame (F+4).

N is a function of the device configuration, as described in Table 7-4.

Figure 7-11 Exit SPD Mode

See the Section 6.6 table for timing specifications for this operating mode.