The 32-CLK, dual-SDO mode is the default mode supported by the device. This mode can also be selected by writing CFR.B11 = 0 and CFR.B10 = 0.

In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B conversion result. Figure 7-6 shows a detailed timing diagram for this mode.

Figure 7-6 32-CLK, Dual-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The device converts the sampled analog input during the conversion time (t_CONV). SDO_A and SDO_B read 0 during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode. The device outputs the MSBs of ADC_A and ADC_B on the SDO_A and SDO_B pins, respectively, on the 16th SCLK falling edge. As shown in Table 7-9, the subsequent SCLK falling edges are used to shift out the rest of the bits of the conversion result.

In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

See the Section 6.6 table for timing specifications specific to this serial interface mode.