As shown in Figure 7-12, the minimum number of SCLK falling edges (N) that must be provided between the beginning and end of the frame depends on the serial interface mode. The SCLK falling edges (N) program the device and retrieve the conversion result. If CS is brought high before the expected number of SCLK falling edges are provided, the current frame is aborted and the device starts sampling the new analog input signal.

If frame (F) is aborted, then the register write operation attempted in frame (F) is considered invalid and the internal registers are not updated. The device continues to have the same configuration in frame (F+1) from frame (F).

The output data bits latched before the CS rising edge are still valid data that correspond to sample N.

Figure 7-12 Frame Abort, Reconversion, or Short-Cycling Feature

See the Section 6.6 table for timing specifications for this operating mode.