米6体育平台手机版

ZHCSCM5B October 2013 – August 2014 ADS7254 , ADS7854 , ADS8354

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

RTE|16
- MPQF149D
PW|16
- MPDS361A

散热焊盘机械数据 (封装 | 引脚)

RTE|16
- QFND298F

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8 Detailed Description

8.1 Overview

These devices belong to a family of pin-compatible, dual, high-speed, simultaneous-sampling, analog-to-digital converters (ADCs). The ADS8354, ADS7854, and ADS7254 support fully-differential input signals. The devices provide a simple, serial interface to the host controller and operate over a wide range of analog and digital power supplies.

These devices have two independently programmable internal references to achieve system-level gain error correction. The Functional Block Diagram section provides a functional block diagram of the device.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Reference

The device has two simultaneous sampling ADCs (ADC_A and ADC_B). ADC_A and ADC_B operate with reference voltages V_{REF_A} and V_{REF_B} present on the REFIO_A and REFIO_B pins, respectively. The REFIO_A and REFIO_B pins should be decoupled with the REFGND_A and REFGND_B pins, respectively, with 10-µF decoupling capacitors.

The device supports operation either with an internal or external reference source, as shown in Figure 84. The reference voltage source is determined by setting bit 6 of the configuration register (CFR.B6). Note that this bit is common to ADC_A and ADC_B.

Figure 84. Reference Configurations and Connections

When CFR.B6 is 0, the device shuts down the internal reference source (INTREF) and ADC_A and ADC_B operate on external reference voltages provided by the user on the REFIO_A and REFIO_B pins, respectively.

When CFR.B6 is 1, the device operates with the internal reference source (INTREF) connected to REFIO_A and REFIO_B via DAC_A and DAC_B, respectively. In this configuration, V_{REF_A} and V_{REF_B} can be changed independently by writing to the respective user-programmable registers, REFDAC_A and REFDAC_B, respectively. Refer to the REFDAC Registers (REFDAC_A and REFDAC_B) section for more details.

8.3.2 Analog Inputs

The ADS8354, ADS7854, and ADS7254 support fully-differential analog input signals on both ADC channels. These inputs are sampled and converted simultaneously by the two ADCs, ADC_A and ADC_B. ADC_A samples and converts (V_{AINP_A} – V_{AINM_A}), and ADC_B samples and converts (V_{AINP_B} – V_{AINM_B}).

Figure 85a and Figure 85b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively. Series resistance, R_S, represents the on-state sampling switch resistance (typically 50 Ω) and C_SAMPLE is the device sampling capacitor (typically 40 pF).

Figure 85. Equivalent Circuit for the Analog Input Pins

8.3.2.1 Analog Input: Full-Scale Range Selection

The full-scale range (FSR) supported at the analog inputs of the device is programmable with bit B9 of the configuration register (CFR.B9). This bit is common for both ADCs (ADC_A and ADC_B). The FSR is given by Equation 1 and Equation 2 :

Equation 1. For CFR.B9 = 0, FSR_ADC_A = ±V_{REF_A} and FSR_ADC_B = ±V_{REF_B}

Equation 2. For CFR.B9 = 1, FSR_ADC_A = ±2 × V_{REF_A} and FSR_ADC_B = ±2 × V_{REF_B}

where

V_{REF_A} and V_{REF_B} are the reference voltages going to ADC_A and ADC_B, respectively (as described in the Reference section).

Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers and CFR.B9, the maximum dynamic range of the ADC can be used.

Note that while using CFR.B9 set to 1, care must be taken so that the ADC analog supply (AVDD) is as in Equation 3 and Equation 4:

Equation 3. 2 × V_{REF_A} ≤ AVDD ≤ AVDD(max)

Equation 4. 2 × V_{REF_B} ≤ AVDD ≤ AVDD(max)

8.3.2.2 Analog Input: Common-Mode Voltage Range

The ADS8354, ADS7854, and ADS7254 support fully-differential input signals. Equation 5 and Equation 6 provide the common-mode voltage for the ADC_A and ADC_B differential inputs.

Equation 5. V_{CM_A} = FSR_ADC_A / 2

Equation 6. V_{CM_B} = FSR_ADC_B / 2

The various input configurations supported by the device are shown in Table 1.

Table 1. Input Configurations

INPUT RANGE SELECTION	INPUT COMMON-MODE RANGE	CONNECTION DIAGRAM
CFR.B9 = 0 (FSR_ADC_A = ±V_{REF_A}) (FSR_ADC_B = ±V_{REF_B})
CFR.B9 = 1 (FSR_ADC_A = ±2 × V_{REF_A}) (FSR_ADC_B = ±2 × V_{REF_B})

8.3.3 Transfer Function

The device output is in twos compliment format. Device resolution for a fully-differential input is calculated by Equation 7:

Equation 7. 1 LSB = (2 × FSR_ADC_x) / (2^N)

where

N = 16 (ADS8354), 14 (ADS7854), or 12 (ADS7254)
FSR_ADC_x is the full-scale input range of the ADC (refer to the Analog Input section for more details)

Table 2 shows the different input voltages and the corresponding output codes from the device.

Table 2. Transfer Characteristics

INPUT VOLTAGE (AINP_x – AINM_x), ±V_REF RANGE	INPUT VOLTAGE (AINP_x – AINM_x), ±2 × V_REF RANGE	INPUT VOLTAGE	OUTPUT CODE (Hex)
INPUT VOLTAGE (AINP_x – AINM_x), ±V_REF RANGE	INPUT VOLTAGE (AINP_x – AINM_x), ±2 × V_REF RANGE	INPUT VOLTAGE	CODE	ADS8354	ADS7854	ADS7254
< – V_{REF_x}	< –2 × V_{REF_x}	NFSC	NFSC	8000	2000	800
–V_{REF_x} + 1 LSB	–2 × V_{REF_x} + 1 LSB	NFSR	NFSC + 1	8001	2001	801
–1 LSB	–1 LSB	–1 LSB	MC	FFFF	3FFF	FFF
0	0	0	PLC	0000	0000	000
> V_{REF_x} – 1 LSB	> 2 × V_{REF_x} – 1 LSB	PFSR – 1 LSB	PFSC	7FFF	1FFF	7FF

Figure 86 shows the ideal transfer characteristics for the device.

Figure 86. Ideal Transfer Characteristics for a Fully-Differential Analog Input

8.4 Device Functional Modes

The device provides three user-programmable registers: the configuration register (CFR), the REFDAC_A register, and the REFDAC_B register. These registers support write (refer to the Write to User Programmable Registers section) and readback (refer to the Reading User-Programmable Registers section) operations and allow the user to customize ADC behavior for specific application requirements.

The device supports four interface modes (refer to the Conversion Data Read section), two low-power modes (refer to the Low-Power Modes section), and short-cycling/reconversion feature (refer to the Frame Abort, Reconversion, or Short-Cycling section).

8.5 Register Maps and Serial Interface

8.5.1 Serial Interface

The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device.

The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. Between the start and end of the frame, a minimum of N SCLK falling edges must be provided to validate the read or write operation. As shown in Table 3, N depends upon the interface mode used to read the conversion result. When N SCLK falling edges are provided, the write operation attempted in the frame is validated and the internal user-programmable registers are updated on the subsequent CS rising edge. This CS rising edge also ends the frame.

Table 3. SCLK Falling Edges for a Valid Write Operation

INTERFACE MODE	MINIMUM SCLK FALLING EDGES REQUIRED TO VALIDATE WRITE OPERATION N
32-CLK, dual-SDO mode (default). See the 32-CLK, Dual-SDO Mode section.	32
32-CLK, single-SDO mode. See the 32-CLK, Single-SDO Mode section.	48
16-CLK, dual-SDO mode. See the 16-CLK, Dual-SDO Mode section.	16
16-CLK, single SDO mode. See the 16-CLK, Single SDO Mode section.	32

If CS is brought high before providing N SCLK falling edges, the write operation attempted in the frame is not valid. Refer to the Frame Abort, Reconversion, or Short-Cycling section for more details.

8.5.2 Write to User Programmable Registers

The device features three user-programmable registers: the configuration register (CFR), the REFDAC_A register, and the REFDAC_B register. These registers can be written with the device SDI pin. The first 16 bits of data on SDI are latched into the device on the first 16 SCLK falling edges. However, the new configuration takes effect only when the read or write operation is validated. If these registers are not required to update, SDI must remain low during the respective frames.

The first four SDI data bits (B[15:12]) determine what operation is performed (that is, either a read or write operation or no operation), which register address the operation uses, and the function of the next 12 SDI data bits (B[11:0]). Table 4 lists the various combinations supported for B[15:12].

Table 4. Data Write Operation

B15	B14	B13	B12	OPERATION	FUNCTION OF BITS B[11:0]
0	0	0	0	No operation is performed	These bits are ignored
0	0	0	1	REFDAC_A read	000h; see the Reading User-Programmable Registers section
0	0	1	0	REFDAC_B read	000h; see the Reading User-Programmable Registers section
0	0	1	1	CFR read	000h; see the Reading User-Programmable Registers section
1	0	0	0	CFR write	See the Configuration Register (CFR) section
1	0	0	1	REFDAC_A write	See the REFDAC_A section
1	0	1	0	REFDAC_B write	See the REFDAC_B section
1	0	1	1	No operation is performed	These bits are ignored
X	1	X	X	No operation is performed	These bits are ignored

8.5.2.1 Configuration Register (CFR)

The device operation configuration is controlled by the configuration register (CFR) status. Data written into the CFR in a valid frame (F) determine the device configuration for frame (F+1). The bit functions are outlined in Figure 87. On power-up, all bits in the CFR default to 0.

Figure 87. CFR Bit Functions

15	14	13	12	11	10	9	8
WRITE/READ	0	ADDR1	ADDR0	RD_CLK_ MODE	RD_DATA_ LINES	INPUT_RANGE	0
7	6	5	4	3	2	1	0
0	REF_SEL	STANDBY	0	0	0	0	0

Table 5. Configuration Register (CFR) Field Descriptions

Bit	Field	Type	Reset	Description
15	WRITE/READ	W	0h	These bits select the user-programmable register. 1000 = Select this combination to write to the CFR register and to enable bits 11:0
14	0	R/W	0h
13	ADDR1	R/W	0h
12	ADDR0	R/W	0h
11	RD_CLK_MODE	R/W	0h	This bit provides clock mode selection for the serial interface. 0 = Selects 32-CLK mode (default) 1 = Selects 16-CLK mode (Note that the ADS8354 only supports 32-CLK mode. This bit is ignored for the ADS8354.)
10	RD_DATA_LINES	R/W	0h	This bit provides data line selection for the serial interface. 0 = Use SDO_A to output ADC_A data and SDO_B to output of ADC_B data (default) 1 = Use only SDO_A to output of ADC_A data followed by ADC_B data
9	INPUT_RANGE	R/W	0h	This bit selects the maximum input range for the ADC as a function of the reference voltage provided to the ADC. See the Analog Inputs section for more details. 0 = FSR equals ±V_REF 1 = FSR equals ±2 × V_REF
8:7	0	R/W	0h	This bit must be set to 0 (default)
6	REF_SEL	R/W	0h	This bit selects the ADC reference voltage source. Refer to the Reference section for more details. 0 = Use external reference (default) 1 = Use internal reference
5	STANDBY	W	0h	This bit is used by the device to enter or exit STANDBY mode. Refer to the STANDBY Mode section for more details.
4	0	R/W	0h	This bit must be set to 0 (default)
3:0	0	R/W	0h	These bits must be set to 0 (default)

8.5.2.2 REFDAC Registers (REFDAC_A and REFDAC_B)

The REFDAC registers, bit functions, and resolution information are described in this section.

Figure 88. REFDAC_X Bit Functions

15	14	13	12	11	10	9	8
WRITE/READ	0	ADDR1	ADDR0	D8	D7	D6	D5
7	6	5	4	3	2	1	0
D4	D3	D2	D1	D0	0	0	0

Table 6. REFDAC Registers Field Descriptions

Bit	Field	Type	Reset	Description
15	WRITE/READ	W	0h	These bits select the configurable register address. 1001 = Select this combination to write to the REFDAC_A register 1010 = Select this combination to write to the REFDAC_B register
14	0	R/W	0h
13	ADDR1	R/W	0h
12	ADDR0	R/W	0h
11:3	D[8:0]	R/W	0h	Data to program the individual DAC output voltage. Note: These bits are valid only for bits 15:12 = 1001 or bits 15:12 = 1010. Table 7 shows the relationship between the REFDAC_x programmed value and the DAC_x output voltage.
2:0	0	R/W	0h	This bit must be set to 0 (default)

Table 7. REFDAC Settings

REFDAC_x VALUE (Bits 11:3 in Hex)	B[2:0]	Typical DAC_x OUPTUT VOLTAGE (V)⁽¹⁾
1FF (default)	000	2.5000
1FE	000	2.4989
1FD	000	2.4978
—	—	—
1D7	000	2.45
—	—	—
1AE	000	2.40
—	—	—
186	000	2.35
—	—	—
15D	000	2.30
—	—	—
134	000	2.25
—	—	—
10C	000	2.20
—	—	—
0E3	000	2.15
—	—	—
0BA	000	2.10
—	—	—
091	000	2.05
—	—	—
069	000	2.00
—	—	—
064 to 000	000	Do not use

(1) Actual output voltage may vary by a few millivolts from the specified value. To obtain the desired output voltage, TI recommends starting with the specified register setting and then experimenting with five codes on either side of the specified register setting.

8.5.3 Data Read Operation

The device supports two types of read operations: reading user-programmable registers and reading conversion results.

8.5.3.1 Reading User-Programmable Registers

The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B. Figure 89 shows a detailed timing diagram for this operation.

Note that N is a function of the device configuration, as described in Table 3.

Figure 89. Register Readback Timing

To readback the user-programmable register settings, the appropriate control word should be transmitted to the device during frame (F+1), as shown in Table 8. Frame (F+1) must have at least 48 SCLK falling edges.

Table 8. Control Word to Readback User-Programmable Registers

USER-PROGRAMMABLE REGISTER	CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
USER-PROGRAMMABLE REGISTER	B[15:12] (Binary)	B[11:0] (Hex)
CFR	0011b	000h
REFDAC_A	0001b	000h
REFDAC_B	0010b	000h

Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 9) and then outputs 0s for any subsequent SCLK falling edges. The SDO_B pin outputs 0s for all the SCLK falling edges.

Table 9. Register Data Read Back

USER-PROGRAMMABLE REGISTER	DATA READ ON SDO-A IN FRAME (F+2)
USER-PROGRAMMABLE REGISTER	R15	R14	R13	R12	R11	—	R3	R2	R1	R0
CFR	0	0	1	1	CFG.B11	—	CFG.B3	CFG.B2	CFG.B1	CFG.B0
REFDAC_A	0	0	0	1	REFDAC_A.D8	—	REFDAC_A.D0	0	0	0
REFDAC_B	0	0	1	0	REFDAC_B.D8	—	REFDAC_B.D0	0	0	0

8.5.3.2 Conversion Data Read

The device provides four different interface modes to the user for reading the conversion result. These modes offer flexible hardware connections and firmware programming. Table 10 shows how to select one of the four interface modes.

Table 10. Interface Mode Selection

CFR.B11	CFR.B10	INTERFACE MODE	MINIMUM SCLK FALLING EDGES REQUIRED TO VALIDATE WRITE OPERATION N
0	0	32-CLK, dual-SDO mode (default)	32
0	1	32-CLK, single-SDO mode	48
1	0	16-CLK, dual-SDO mode	16
1	1	16-CLK, single SDO mode	32

In the 32-CLK interface modes, the device uses an internal clock to convert the sampled analog signal. The conversion is completed during the first 16 periods of SCLK and the conversion result can be read on the subsequent SCLK falling edges. All devices in the family (that is, ADS8354, ADS7854, and ADS7254) support the 32-CLK interface modes.

In addition to the 32-CLK interface modes, the ADS7854 and ADS7254 also support the 16-CLK interface modes. By using the 16-CLK interface modes, the same throughput can be achieved at much lower SCLK speeds.

The following sections detail the various interface modes supported by the device.

8.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)

The 32-CLK, dual-SDO mode is the default mode supported by all devices. This mode can also be selected by writing CFR.B11 = 0 and CFR.B10 = 0.

In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B conversion result. Figure 90 shows a detailed timing diagram for this mode.

Figure 90. 32-CLK, Dual-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The device converts the sampled analog input during the conversion time (t_CONV). SDO_A and SDO_B read 0 during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode. The device outputs the MSBs of ADC_A and ADC_B on SDO_A and SDO_B pins, respectively, on the 16th SCLK falling edge. The subsequent SCLK falling edges are used to shift out the rest of the bits of the conversion result, as shown in Table 11.

Table 11. Data Launch Edge

DEVICE	PINS	LAUNCH EDGE
		CS	SCLK											CS
		↓	↓1	—	↓15	↓16	—	↓27	↓28	↓29	↓30	↓31	↓32 ...	↑
ADS8354	SDO-A	0	0	—	0	D15_A	—	D4_A	D3_A	D2_A	D1_A	D0_A	0 ...	Hi-Z
ADS8354	SDO-B	0	0	—	0	D15_B	—	D4_B	D3_B	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7854	SDO-A	0	0	—	0	D13_A	—	D2_A	D1_A	D0_A	0	0	0 ...	Hi-Z
ADS7854	SDO-B	0	0	—	0	D13_B	—	D2_B	D1_B	D0_B	0	0	0 ...	Hi-Z
ADS7254	SDO-A	0	0	—	0	D11_A	—	D0_A	0	0	0	0	0 ...	Hi-Z
ADS7254	SDO-B	0	0	—	0	D11_B	—	D0_B	0	0	0	0	0 ...	Hi-Z

In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 12 for timing specifications specific to this serial interface mode.

Table 12. 32-CLK, Dual-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TIMING REQUIREMENTS
t_CLK	CLOCK period	ADS8354	41.66			ns
		ADS7854	29.4			ns
		ADS7254	29.4			ns
t_ACQ	Acquisition time			33 × t_CLK – t_CONV		ns
TIMING SPECIFICATIONS
t_CONV	Conversion time	ADS8354			640	ns
		ADS7854			450	ns
		ADS7254			450	ns

8.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)

The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect (NC) pin.

This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. Figure 91 shows a detailed timing diagram for this mode.

Figure 91. 32-CLK, Single-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device converts the sampled analog input during the conversion time (t_CONV). SDO_A reads 0 during this period. After competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. The subsequent SCLK falling edges are used to shift out the conversion result of ADC_A followed by the conversion result of ADC_B on the SDO_A pin, as shown in Table 13.

Table 13. Data Launch Edge

DEVICE	PIN	LAUNCH EDGE
		CS	SCLK																		CS
		↓	↓1	—	↓15	↓16	—	↓27	↓28	↓29	↓30	↓31	↓32	—	↓43	↓44	↓45	↓46	↓47	↓48 ...	↑
ADS8354	SDO-A	0	0	—	0	D15_A	—	D4_A	D3_A	D2_A	D1_A	D0_A	D15_B	—	D4_B	D3_B	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7854	SDO-A	0	0	—	0	D13_A	—	D2_A	D1_A	D0_A	0	0	0	—	D2_B	D1_B	D0_B	0	0	0 ...	Hi-Z
ADS7254	SDO-A	0	0	—	0	D11_A	—	D0_A	0	0	0	0	0	—	D0_B	0	0	0	0	0 ...	Hi-Z

In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 14 for timing specifications specific to this serial interface mode.

Table 14. 32-CLK, Single-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TIMING REQUIREMENTS
t_CLK	CLOCK period	ADS8354	41.66			ns
		ADS7854	29.4			ns
		ADS7254	29.4			ns
t_ACQ	Acquisition time			49 × t_CLK – t_CONV		ns
TIMING SPECIFICATIONS
t_CONV	Conversion time	ADS8354			640	ns
		ADS7854			450	ns
		ADS7254			450	ns

8.5.3.2.3 16-CLK, Dual-SDO Mode (CFR.B11 = 1, CFR.B10 = 0)

The 16-CLK, dual-SDO mode is designed to support the maximum throughput at lower SCLK frequencies. This interface mode is not supported by the ADS8354.

For the ADS7854 and ADS7254, this interface mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 0. In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B conversion result. Figure 92 shows a detailed timing diagram for this mode.

Figure 92. 16-CLK, Dual-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins. The subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as shown in Table 15.

The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.

Table 15. Data Launch Edge

DEVICE	PINS	LAUNCH EDGE
		CS	SCLK							CS
		↓	↓1	↓2	—	↓13	↓14	↓15	↓16 ...	↑
ADS7854	SDO-A	0	0	D13_A	—	D2_A	D1_A	D0_A	0 ...	Hi-Z
ADS7854	SDO-B	0	0	D13_B	—	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7254	SDO-A	0	0	D11_A	—	D0_A	0	0	0 ...	Hi-Z
ADS7254	SDO-B	0	0	D11_B	—	D0_B	0	0	0 ...	Hi-Z

In this mode, at least 16 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 16 for timing specifications specific to this serial interface mode.

Table 16. 16-CLK, Dual-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	UNIT
TIMING REQUIREMENTS
t_CLK	CLOCK period	ADS7854	55.5		ns
t_CLK	CLOCK period	ADS7254	55.5		ns
t_ACQ	Acquisition time	ADS7854		4 × t_CLK	ns
t_ACQ	Acquisition time	ADS7254		6 × t_CLK	ns
TIMING SPECIFICATIONS
t_CONV	Conversion time	ADS7854		14 × t_CLK	ns
t_CONV	Conversion time	ADS7254		12 × t_CLK	ns

8.5.3.2.4 16-CLK, Single-SDO Mode (CFR.B11 = 1, CFR.B10 = 1)

The 16-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) and a lower-speed clock to read the conversion results of both ADCs. This interface mode is not supported by the ADS8354.

For the ADS7854 and ADS7254, this mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 1. The SDO_A pin is used to output the conversion results of both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect (NC) pin. Figure 93 shows a detailed timing diagram for this mode.

Figure 93. 16-CLK, Single-SDO Mode Timing Diagram

A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as shown in Table 17.

The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.

Table 17. Data Launch Edge

DEVICE	PIN	LAUNCH EDGE
		CS	SCLK														CS
		↓	↓1	↓2	—	↓13	↓14	↓15	↓16	↓17	↓18	—	↓29	↓30	↓31	↓32 ...	↑
ADS7854	SDO-A	0	0	D13_A	—	D2_A	D1_A	D0_A	0	0	D13_B	—	D2_B	D1_B	D0_B	0 ...	Hi-Z
ADS7254	SDO-A	0	0	D11_A	—	D0_A	0	0	0	0	D11_B	—	D0_B	0	0	0 ...	Hi-Z

In this mode, at least 32 SCLK falling edges must be given to validate the read/write frame. A CS rising edge ends the frame and puts the serial bus into 3-state.

Refer to Table 18 for timing specifications specific to this serial interface mode.

Table 18. 16-CLK, Single-SDO Interface Specific Timing

PARAMETER		TEST CONDITIONS	MIN	TYP	UNIT
TIMING REQUIREMENTS
t_CLK	CLOCK period	ADS7854	55.5		ns
t_CLK	CLOCK period	ADS7254	55.5		ns
t_ACQ	Acquisition time	ADS7854		19 × t_CLK	ns
t_ACQ	Acquisition time	ADS7254		21 × t_CLK	ns
TIMING SPECIFICATIONS
t_CONV	Conversion time	ADS7854		14 × t_CLK	ns
t_CONV	Conversion time	ADS7254		12 × t_CLK	ns

8.5.4 Low-Power Modes

In normal mode of operation, all internal circuits of the device are always powered up and the device is always ready to commence a new conversion. This mode enables the device to support the rated throughput. The device also supports two low-power modes to optimize the power consumption at lower throughputs: STANDBY mode and software power-down (SPD) mode.

8.5.4.1 STANDBY Mode

The device supports a STANDBY mode of operation where some of the internal circuits of the device are powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster power-up to a normal mode of operation.

As shown in Figure 94, a valid write operation in frame (F) to program the configuration register with B5 set to 1 (CFR.B5 = 1) places the device into a STANDBY mode of operation on the following CS rising edge. While in STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high.

To remain in STANDBY mode, SDI must remain low in the subsequent frames.

Note that N is a function of the device configuration, as described in Table 3.

Figure 94. Enter STANDBY Mode

As shown in Figure 95, a valid write operation in frame (F+3) by writing the configuration register with B5 set to 0 (CFR.B5 = 0) brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must have at least 48 SCLK falling edges.

After exiting the STANDBY mode, a delay of t_{PU_STDBY} must elapse for the internal circuits to fully power-up and resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the CFR.B[11:6] bits programmed during frame (F+3).

Note that N is a function of the device configuration, as described in Table 3.

Figure 95. Exit STANDBY Mode

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

8.5.4.2 Software Power-Down (SPD) Mode

In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down. However, the contents of the REFDAC_A and REFDAC_B registers are retained.

As shown in Figure 96, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS signal.

To remain in SPD mode, SDI must remain high in subsequent frames.

Figure 96. Enter SPD Mode

As shown in Figure 97, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be kept low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising edge following frame (F+3). After frame (F+3), a delay of t_{PU_SPD} must elapse before programming the configuration register.

A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at least 48 SCLK falling edges. The output data in frame (F+4) should be discarded.

Note that N is a function of the device configuration, as described in Table 3.

Figure 97. Exit SPD Mode

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.

8.5.5 Frame Abort, Reconversion, or Short-Cycling

As discussed inFigure 98, the minimum number of SCLK falling edges (N) that must be provided between the beginning and end of the frame depends on the serial interface mode. The SCLK falling edges (N) program the device and retrieve the conversion result. If CS is brought high before the expected number of SCLK falling edges are provided, the current frame is aborted and the device starts sampling the new analog input signal.

If frame (F) is aborted, then the register write operation attempted in frame (F) is considered invalid and the internal registers are not updated. The device continues to have the same configuration in frame (F+1) from frame (F).

The output data bits latched before the CS rising edge are still valid data that correspond to sample N.

Figure 98. Frame Abort, Reconversion, or Short-Cycling Feature

Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.