8.3.1.1 Analog Inputs

Each ADC is fed by an input multiplexer, as shown in Figure 27. Each multiplexer is used in either a fully-differential 2:1 configuration (as shown in Table 1) or a pseudo-differential 4:1 configuration (as shown in Table 2).

Figure 27. Input Multiplexer Configuration

Channel selection is performed using either the external M0 pin or the C[1:0] bits in the Configuration (CONFIG) register in fully-differential mode, or using the SEQFIFO register in pseudo-differential mode. In either case, changing the multiplexer settings impacts the conversion started with the next CONVST pulse.

The input path for the converter is fully differential and provides a good common-mode rejection of 92 dB at 100 kHz (for the ADS8363). The high CMRR also helps suppress noise in harsh industrial environments.

Each of the 40-pF sample-and-hold capacitors (C_S in Figure 28) is connected through switches to the multiplexer output. Opening the switches holds the sampled data during the conversion process. After the conversion completes, both capacitors are precharged for the duration of one clock cycle to the voltage present at the REFIOx pin. After precharging, the multiplexer outputs are connected to the sampling capacitors again. The voltage at the analog input pin is usually different from the reference voltage; therefore, the sample capacitors must be charged to within one-half LSB for 16-, 14-, or 12-bit accuracy during the acquisition time t_ACQ (see Figure 1 and Figure 2).

Figure 28. Equivalent Analog Input Circuit

Acquisition is indicated with the BUSY signal being low. Acquisition starts by closing the input switches (after finishing the previous conversion and precharging) and finishes with the rising edge of the CONVST signal. If the device operates at full speed, the acquisition time is typically 100 ns.

The minimum –3-dB bandwidth of the driving operational amplifier can be calculated as shown in Equation 1, with n = 16 for the resolution of the ADS8363, n = 14 for the ADS7263, or n = 12 for the ADS7223:

Equation 1.

With t_ACQ = 100 ns, the minimum bandwidth of the driving amplifier is 19 MHz for the ADS8363, 17 MHz for the ADS7263, and 15 MHz for the ADS7223. The required bandwidth can be lower if the application allows a longer acquisition time.

A gain error occurs if a given application does not fulfill the settling requirement shown in Equation 1. However, linearity and THD are not directly affected as a result of precharging the capacitors.

The OPA365 from Texas Instruments is recommended as a driver; in addition to offering the required bandwidth, the OPA365 also provides a low offset and excellent THD performance (see the Application and Implementation section).

The phase margin of the driving operational amplifier is usually reduced by the ADC sampling capacitor. A resistor placed between the capacitor and the amplifier limits this effect; therefore, an internal 100-Ω resistor (R_SER) is placed in series with the switch. The switch resistance (R_SW) is typically 100 Ω; see Figure 28).

An input driver may not be required, if the impedance of the signal source (R_SOURCE) fulfills the requirement of Equation 2:

Equation 2.

where

• n = 16, 14, 12 for the resolution of the ADS8363, ADS7263, and ADS7223, respectively
• C_S = 40-pF sample capacitance
• R_SER = 100-Ω input resistor value
• R_SW = 100-Ω switch resistance value

With t_ACQ = 100 ns, the maximum source impedance must be less than 12 Ω for the ADS8363, less than 40 Ω for the ADS7263, and less than 77 Ω for the ADS7223. The source impedance can be higher if the ADC is used at a lower data rate.

The differential input voltage range of the ADC is ±V_REF, the voltage at the selected REFIOx pin.

The voltage to all inputs must be kept within the 0.3-V limit below AGND and above AVDD, without allowing dc current to flow through the inputs (exceeding these limits causes the internal ESD diodes to conduct, leading to increased leakage current that may damage the device). Current is only necessary to recharge the sample-and-hold capacitors.

Unused inputs must be directly tied to AGND or RGND without the need of a pull-down resistor.

8.3.1.2 Analog-to-Digital Converters (ADCs)

The ADS8363, ADS7263, and ADS7223 include two SAR-type, 1 MSPS, 16-, 14-, and 12-bit ADCs that include sample-and-hold, respectively; see the Functional Block Diagram section.

8.3.1.3 CONVST

The analog inputs are held with the rising edge of the CONVST (conversion start) signal. The setup time of CONVST referred to the next rising edge of CLOCK (system clock) is 12 ns (minimum). The conversion automatically starts with the rising CLOCK edge. Do not issue a rising edge of CONVST during a conversion (that is, when BUSY is high).

RD (read data) and CONVST can be shorted to minimize necessary software and wiring. The RD signal is triggered by the device on the falling edge of CLOCK. Therefore, the combined signals must be activated with the rising CLOCK edge. The conversion then starts with the subsequent rising CLOCK edge. In modes with only SDOA active (that is, in modes II, IV, SII, and SIV), the maximum length of the combined RD and CONVST signal is one clock cycle if the half-clock timing is used.

If CONVST and RD are combined, CS must be low whenever a new conversion starts; however, this condition is not required if RD and CONVST are controlled separately. Note that if FIFO is used, CONVST must be controlled separately from RD.

After completing a conversion, the sample capacitors are automatically precharged to the value of the reference voltage used to significantly reduce the crosstalk among the multiplexed input channels.

8.3.1.4 CLOCK

The ADS8363, ADS7263, and ADS7223 use an external clock with an allowable frequency range that depends on the mode being used. By default (after power-up), the ADC operates in half-clock mode that supports a clock in the range of 0.5 MHz to 20 MHz. In full-clock mode, the ADC requires a clock in the range of 1 MHz to 40 MHz. For maximum data throughput, the clock signal must be continuously running. However, in applications that use the device in burst mode, the clock can be held static low or high upon completion of the read access and before starting a new conversion.

The CLOCK duty cycle must be 50%. However, the device functions properly with a duty cycle between 30% and 70%.

8.3.1.5 RESET

The ADS8363, ADS7263, and ADS7223 feature an internal power-on reset (POR) function. A user-controlled reset can also be issued using SDI register bits A[3:0] (see the Digital section).

8.3.1.6 REFIOx

The ADS8363, ADS7263, and ADS7223 include a low-drift, 2.5-V internal reference source. This source feeds two, 10-bit string DACs that are controlled through registers. As a result of this architecture, the reference voltages at REFIOx are programmable in 2.44-mV steps and can be adjusted to the application requirements without the use of additional external components. The actual output voltage can be calculated using Equation 3, with code being the decimal value of the REFDACx register content:

Equation 3.

The reference DAC has a fixed transition at the code 508 (0x1FC). At this code, the DAC can show a jump of up to 10 mV in the transfer function. Table 3 lists some examples of internal reference DAC settings. However, to ensure proper performance, the REFDACx output voltage must not be programmed below 0.5 V.

A minimum of 22-μF capacitance is required on each REFIOx output to keep the references stable. The settling time is 8 ms (maximum) with the reference capacitor connected. Smaller reference capacitance values reduce the DNL, INL, and ac performance of the device. By default, both reference outputs are disabled and the respective values are set to 2.5 V after power-up.

For applications that use an external reference source, the internal reference can be disabled (default) using the RPD bit in the CONFIG register (see the Digital section). The REFIOx pins are directly connected to the ADC; therefore, the internal switching generates spikes that can be observed at this pin. Therefore, also in this case, an external 22-µF capacitor to the analog ground (AGND) must be used to stabilize the reference input voltage.

Disabled REFIOx pins can be left floating or can be directly tied to AGND or RGND.

Each of the reference DAC outputs can be individually selected as a source for each channel input using the Rxx bits in the REFCM register. Figure 29 shows a simplified block diagram of the internal circuit.

Figure 29. Reference Selection Circuit

Table 4. Supported Operating Modes

8.3.2.1 Mode Selection Pin M0 and M1

The ADS8363, ADS7263, and ADS7223 can be configured to four different operating modes by using mode pins M0 and M1, as shown in Table 5.

The M0 pin sets either manual or automatic channel selection. In Manual mode, CONFIG register bits C[1:0] are used to select between channels CHx0 and CHx1. In Automatic mode, CONFIG register bits C[1:0] are ignored and channel selection is controlled by the device after each conversion. The automatic channel selection is only performed on fully-differential inputs in this case; for pseudo-differential inputs, the internal sequencer controls the input multiplexer.

The M1 pin selects between serial data being transmitted simultaneously on both SDOA and SDOB outputs for each channel, respectively, or using only the SDOA output for transmitting data from both channels (see Figure 31 through Figure 36 and the associated text for more information).

Additionally, the SDI pin is used for controlling device functionality through the internal register; see the Register Maps section for details.

8.3.2.2 Half-Clock Mode (Default Mode After Power-Up and Reset)

The ADS8363, ADS7263, and ADS7223 power up in half-clock mode, in which the ADC requires at least 20 CLOCKs for a complete conversion cycle, including the acquisition phase. The conversion result can only be read during the next conversion cycle. The first output bit is available with the falling RD edge, and the following output data bits are refreshed with the rising edge of CLOCK.

8.3.2.3 Full-Clock Mode (Allowing Conversion and Data Readout Within 1 µs, Supported In Dual Output Modes)

The full-clock mode allows converting data and reading the result within 1µ s. The entire cycle requires 40 CLOCKs. The first output bit is available with the falling RD edge and the following output data bits are refreshed with the falling edge of the CLOCK in this mode.

The full-clock mode can only be used with analog power supply AVDD in the range of 4.5 V to 5.5 V and digital supply DVDD in the range of 2.3 V to 3.6 V. The internal FIFO is disabled in full-clock mode.

8.3.2.4 2-Bit Counter

These devices offers a selectable 2-bit counter (activated using the CE bit in the CONFIG register) that is a useful feature in safety applications. The counter value automatically increments whenever a new conversion result is stored in the output register, indicating a new value. The counter default value after power-up is '01' (followed by '10', '11', '00', '01', and so on); see Figure 40. Because the counter value increments only when a new conversion results are transferred to the output register, this counter is used to verify that the ADC has performed a conversion and the data read is the result of this new conversion (not a old result read multiple times).

Table 6. Power-Down Modes

8.4.1.1 Power-Down Mode

In Power-Down mode (PD[1:0] = '01'), all functional blocks except the digital interface are disabled. In this mode, the current demand is reduced to 5 µA within 20 µs. The wakeup time from Power-Down mode is 8ms when using a reference capacitor of 22 µF. The device goes into Power-Down mode after completing any ongoing conversions.

8.4.1.2 Sleep Mode

In Sleep mode (PD[1:0] = '10'), the device reduces the current demand to approximately 0.9 mA within 10 µs. The device goes into Sleep mode after completing any ongoing conversions.

8.4.1.3 Auto-Sleep Mode

Auto-Sleep mode is almost identical to Sleep mode. The only differences are the method of activating the mode and waking up the device. CONFIG register bits PD[1:0] = '11' are only used to enable or disable this feature. If the Auto-Sleep mode is enabled, the device automatically turns off the biasing after finishing a conversion; thus, the end of conversion actually activates Auto-Sleep mode. If Sequencer mode is used and individual conversion start pulses are chosen (S1 = '0'), the device automatically powers-down after each conversion; in case of a single CONVST pulse starting the sequence (S1 = '1'), power-down is activated upon completion of the entire sequence.

The device wakes up with the next CONVST pulse but the analog input is held in sample mode for another seven clock cycles in half-clock mode, or 14 clock cycles in full-clock mode, before starting the actual conversion (BUSY goes high thereafter); see Figure 30. This time is required to settle the internal circuitry to the required voltage levels. The conversion result is delayed in Auto-Sleep mode; see Figure 36.

In this mode, the current demand is reduced to approximately 1.2 mA within 10 µs.

Figure 30. Actual Conversion Start In Auto-Sleep Mode

8.4.1.4 Reset

To issue a device reset, an RD pulse must be generated along with a control word containing A[3:0] = '0100'. With the completion of this write access, the entire device including the serial interface is forced into reset, interrupting any ongoing conversions, setting the input into acquisition mode, and returning the register contents to their default values. After approximately 20 ns, the serial interface becomes active again. The device also supports an automatic power-up reset (POR) that ensures proper (default) settings of the device.

Table 7. Output Data Format

8.5.2.1 Mode I

With the M0 and M1 pins both set to '0', the device enters manual channel-control operation and outputs data on both SDOA and SDOB, accordingly. The SDI pin can be used to switch between the channels, as explicitly shown in the corresponding timing diagrams. A conversion is initiated by bringing CONVST high.

With the rising edge of CONVST, the device switches asynchronously to the external CLOCK from sample to hold mode, and the BUSY output pin goes high and remains high for the duration of the conversion cycle. On the falling edge of the second CLOCK cycle, the device latches in the channel for the next conversion cycle, depending on the status of CONFIG register bits C[1:0]. CS must be brought low to enable both serial outputs. Data are valid on the falling edge of every 20 clock cycles per conversion. The first two bits are set to '0'. The subsequent data contain the 16-, 14-, or 12-bit conversion result (the most significant bit is transferred first), with trailing zeroes, as shown in Figure 31.

This mode can be used for fully- or pseudo-differential inputs; in both cases, channel information bits are '00' if CID = '0'. Note that FIFO is not available in this mode.

1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.

Figure 31. Mode I Timing
(M0 = '0', M1 = '0', PDE = '0', CID = '1', Fully-Differential Example)

8.5.2.2 Mode II (Half-Clock Mode Only)

With M0 = '0' and M1 = '1', the ADS8363, ADS7263, and ADS7223 also operate in manual channel-control mode and output data on the SDOA pin only when SDOB is set to high impedance. All other pins function in the same manner as they do in Mode I.

In half-clock mode, because 40 clock cycles are required to output the results from both ADCs (instead of 20 cycles if M1 = '0'), the device requires 2.0 μs to perform a complete read cycle. If the CONVST signal is issued every 1.0 μs (required for the RD signal) as in Mode I, every second pulse is ignored, as shown in Figure 32. CONVST and RD signals must not be longer than one clock cycle to ensure proper functionality and avoid corruption of output data.

Full-clock mode is not supported in this operational mode.

The output data consist of a '0', followed by an ADC indicator ('0' for CHAx or '1' for CHBx), and then 16, 14, or 12 bits of conversion result along with any trailing zeroes.

This mode can be used for fully- or pseudo-differential inputs. Channel information is valid in fully-differential mode only if CID = '0' (CID contains correct ADC information when the channel bit is invalid in pseudo-differential mode). Note that FIFO is not available in this mode.

Changes to register bits FE, SR, PDE, and CID are active with the start of the next conversion. with a delay of one read access.

The register settings must be updated using every other RD pulse, aligned either with the one starting the conversion or the one to read the conversion results of channel B, as shown in Figure 32.

1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.

Figure 32. Mode II Timing
(M0 = '0', M1 = '1', PDE = '0', CID = '0', Pseudo-Differential Example)

8.5.2.3 Special Read Mode II (Half-Clock Mode Only)

For Mode II, a special read mode is available in the ADS8363, ADS7263, and ADS7223 where both data results can be read out triggered by a single RD pulse (see Figure 33). To activate this mode, The SR bit in the CONFIG register must be set to '1' (see Table 8). The CONVST and RD pins can still be tied together but are issued every 40 CLOCK cycles instead of 20. Output data are presented on SDOA only when SDOB is held in 3-state.

The RD signal in this mode must not be longer than one clock cycle to avoid corruption of output data.

This special mode can be used for fully- or pseudo-differential inputs. Channel information is valid in fully-differential mode only if CID = '0' (CID contains correct ADC information when the channel bit is invalid in pseudo-differential mode). Note that FIFO is not available in this mode.

1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.

Figure 33. Special Read Mode II Timing Diagram
(M0 = '0', M1 = '1', PDE = '0', SR = '1', CID = '0', Fully-Differential Example)

8.5.2.4 Mode III

With M0 = '1' and M1 = '0', the device automatically cycles between the differential inputs (CONFIG register bits C[1:0] are ignored) when offering the conversion result of CHAx on SDOA and the conversion result of CHBx on SDOB, as shown in Figure 34.

Output data consist of a channel indicator ('0' for CHx0, or '1' for CHx1), followed by a '0', and then 16, 14, or 12 bits of conversion result along with any trailing zeroes.

This mode can be used for fully- or pseudo-differential inputs (in pseudo-differential mode the sequencer is used to control the input multiplexer). Channel information is available in fully-differential mode only if CID = '0' (CID is forced to '1' in pseudo-differential mode).

The internal FIFO is available in this mode; when used, a single read pulse allows for reading of all stored conversion data. The FIFO must be completely filled when used for the first time in order to ensure proper functionality.

1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.

Figure 34. Mode III Timing
(M0 = '1', M1 = '0', PDE = '0', CID = '0', Fully-Differential Example)

8.5.2.5 Fully-Differential Mode IV (Half-Clock Mode Only)

In the same way as Mode II, Mode IV uses the SDOA output line exclusively to transmit data when the differential channels are switched automatically. Following the first conversion after M1 goes high, the SDOB output 3-states, as shown in Figure 35.

Output data consist of a channel indicator ('0' for CHx0, or '1' for CHx1), followed by the ADC indicator ('0' for CHAx or '1' for CHBx), and then 16 or 14 bits of conversion result, ending with '00' for the ADS8363, '0000' for the ADS7263, or '000000' for the ADS7223.

CONVST and RD signals must not be longer than one clock cycle to ensure proper functionality and avoid corruption of output data.

Full-clock mode is not supported in this operational mode.

Channel information is available in fully-differential mode if CID = '0'. In pseudo-differential mode, the sequencer controls the channel selection in this mode and must be set appropriately using the SEQFIFO register. The internal FIFO is not available in this mode.

Changes to CONFIG register bits FE, SR, PDE, and CID are active with the start of the next conversion with a delay of one read access.

The register settings must be updated using every other RD pulse (aligned either with the one starting the conversion or the one to read the conversion results of channel B; compare with Figure 32).

1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.

Figure 35. Fully-Differential Mode IV Timing
(M0 = '1', M1 = '1', PDE = '0', and CID = '0' Example)

8.5.2.6 Special Mode IV (Half-Clock Mode Only)

As with Special Mode II, these devices also offer a special read mode for Mode IV, where both data results of a conversion can be read by triggering a single RD pulse, as shown in Figure 36. Additionally, in this case, the SR bit in the CONFIG register must be set to '1' and the CONVST and RD pins can still be tied together, but are issued every 40 CLOCK cycles instead of 20. The RD signal in this mode must not be longer than one clock cycle to avoid corruption of output data.

Data are available on the SDOA pin, accordingly.

If auto-sleep power-down mode is enabled, the conversion results are presented during the next conversion, as shown in Figure 36.

This mode can be used for fully- or pseudo-differential inputs (note that in pseudo-differential mode, the sequencer is used to control the input multiplexer); channel information is available if CID = '0' in fully-differential mode only (CID forced to '1' in pseudo-differential mode).

The internal FIFO is available in this mode; when used, a single read pulse allows for reading of all stored conversion data. The FIFO must be completely filled when used for the first time in order to ensure proper functionality.

1. The ADS7263 and ADS7223 output data with the MSB located as the ADS8363 and the last 2 or 4 bits are '0'.

Figure 36. Special Read Mode IV Timing
(M0 = '1', M1 = '1', PDE = '0', SR = '1', CID = '0', Fully-Differential Example)

Table 9. Conversion Result Read Out In FIFO Mode