SBAS531D December   2010  – February 2016 ADS8555

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Serial Interface Timing Requirements
    7. 6.7 Parallel Interface Timing Requirements (Read Access)
    8. 6.8 Parallel Interface Timing Requirements (Write Access)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog
        1. 7.3.1.1 Analog Inputs
        2. 7.3.1.2 Analog-to-Digital Converter (ADC)
        3. 7.3.1.3 Conversion Clock
        4. 7.3.1.4 CONVST_x
        5. 7.3.1.5 BUSY/INT
        6. 7.3.1.6 Reference
      2. 7.3.2 Digital
        1. 7.3.2.1 Device Configuration
        2. 7.3.2.2 Parallel Interface
        3. 7.3.2.3 Serial Interface
        4. 7.3.2.4 Output Data Format
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Mode
      2. 7.4.2 Software Mode
      3. 7.4.3 Daisy-Chain Mode (In Serial Mode Only)
      4. 7.4.4 Sequential Mode (In Software Mode With External Conversion Clock Only)
      5. 7.4.5 Reset and Power-Down Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Register (CR); Default Value = 0x000003FF
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Measurement of Electrical Variables in a 3-Phase Power System
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, HVDD to AGND –0.3 18 V
Supply voltage, HVSS to AGND –18 0.3 V
Supply voltage, AVDD to AGND –0.3 6 V
Supply voltage, BVDD to BGND –0.3 6 V
Analog input voltage HVSS – 0.3 HVDD + 0.3 V
Reference input voltage with respect to AGND AGND – 0.3 AVDD + 0.3 V
Digital input voltage with respect to BGND BGND – 0.3 BVDD + 0.3 V
Ground voltage difference AGND to BGND ±0.3 V
Input current to all pins except supply –10 10 mA
Maximum virtual junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage, AVDD to AGND 4.5 5 5.5 V
Supply voltage, BVDD to BGND Low-voltage levels 2.7 3 3.6 V
5-V logic levels 4.5 5 5.5
Input supply voltage, HVDD to AGND Input range = ±2 × VREF 2 × VREF 16.5 V
Input range = ±4 × VREF 4 × VREF 16.5
Input supply voltage, HVSS to AGND Input range = ±2 × VREF –16.5 –2 × VREF V
Input range = ±4 × VREF –16.5 –4 × VREF
Reference input voltage (VREF) 0.5 2.5 3 V
Analog inputs
(also see the Analog Inputs section)		 Input range = ±2 × VREF –2 × VREF 2 × VREF V
Input range = ±4 × VREF –4 × VREF 4 × VREF
Operating ambient temperature, TA –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) ADS8555 UNIT
PM (LQFP)
64 PINS
RθJA Junction-to-ambient thermal resistance 48 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16 °C/W
RθJB Junction-to-board thermal resistance N/A °C/W
ψJT Junction-to-top characterization parameter N/A °C/W
ψJB Junction-to-board characterization parameter N/A °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range of –40°C to 125°C, AVDD = 4.5 V to 5.5 V, BVDD = 2.7 V to 5.5 V, HVDD = 10 V to 15 V, HVSS = –15 V to –10 V, VREF = 2.5 V (internal), and fDATA = maximum (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
DC ACCURACY
Resolution 16 Bits
No missing codes 16 Bits
Integral linearity error INL At TA = –40°C to 85°C –3 ±1.5 3 LSB
At TA = –40°C to 125°C –4 ±1.5 4
Differential linearity error DNL At TA = –40°C to 85°C –1 ±0.75 1.5 LSB
At TA = –40°C to 125°C –1 ±0.75 2
Offset error –4 ±0.8 4 mV
Offset error drift ±3.5 μV/°C
Gain error Referenced to voltage at REFIO –0.75 ±0.25 0.75 %FSR
Gain error drift Referenced to voltage at REFIO ±6 ppm/°C
Power-supply rejection ratio PSRR At output code FFFFh, related to AVDD 60 dB
SAMPLING DYNAMICS
Acquisition time tACQ 280 ns
Conversion time per ADC tCONV 1.26 μs
Internal conversion clock period tCCLK 18.5 tCCLK
68 ns
Throughput rate fDATA Parallel interface, internal clock and reference 630 kSPS
Serial interface, internal clock and reference 450
AC ACCURACY
Signal-to-noise ratio SNR At fIN = 10 kHz, TA = –40°C to 85°C 90 91.5 dB
At fIN = 10 kHz, TA = –40°C to 125°C 89 91.5
Signal-to-noise ratio + distortion SINAD At fIN = 10 kHz, TA = –40°C to 85°C 87 89.5 dB
At fIN = 10 kHz, TA = –40°C to 125°C 86.5 89.5
Total harmonic distortion(2) THD At fIN = 10 kHz, TA = –40°C to 85°C –94 –90 dB
At fIN = 10 kHz, TA = –40°C to 125°C –94 –89.5
Spurious-free dynamic range SFDR At fIN = 10 kHz, TA = –40°C to 85°C 90 95 dB
At fIN = 10 kHz, TA = –40°C to 125°C 89.5 95
Channel-to-channel isolation At fIN = 10 kHz 100 dB
–3-dB small-signal bandwidth Input range = ±4 × VREF 48 MHz
Input range = ±2 × VREF 24
ANALOG INPUT
Bipolar full-scale range CHXX RANGE pin, RANGE bit = 0 –4 × VREF 4 × VREF V
RANGE pin, RANGE bit = 1 –2 × VREF 2 × VREF
Input capacitance Input range = ±4 × VREF 10 pF
Input range = ±2 × VREF 20
Input leakage current No ongoing conversion ±1 μA
Aperture delay 5 ns
Aperture delay matching Common CONVST for all channels 250 ps
Aperture jitter 50 ps
EXTERNAL CLOCK INPUT (XCLK)
External clock frequency fXCLK An external reference must be used for fXCLK > fCCLK 1 18 20 MHz
External clock duty cycle 45% 55%
REFERENCE VOLTAGE OUTPUT (REFOUT)
Reference voltage VREF 2.5-V operation, REFDAC = 0x3FF 2.485 2.5 2.515 V
2.5-V operation, REFDAC = 0x3FF at 25°C 2.496 2.5 2.504
3-V operation, REFDAC = 0x3FF 2.985 3 3.015
3-V operation, REFDAC = 0x3FF at 25°C 2.995 3 3.005
Reference voltage drift dVREF/dT ±10 ppm/°C
Power-supply rejection ratio PSRR 73 dB
Output current IREFOUT With dc current –2 2 mA
Short circuit current(3) IREFSC 50 mA
Turnon settling time tREFON 10 ms
External load capacitance At CREF_x pins 4.7 10 μF
At REFIO pins 100 470 nF
Tuning range REFDAC Internal reference output voltage range 0.2 × VREF VREF V
REFDAC resolution 10 Bits
REFDAC differential nonlinearity DNLDAC –1 ±0.1 1 LSB
REFDAC integral nonlinearity INLDAC –2 ±0.1 2 LSB
REFDAC offset error VOSDAC VREF = 0.5 V (DAC = 0x0CC) –4 ±0.65 4 LSB
REFERENCE VOLTAGE INPUT (REFIN)
Reference input voltage VREFIN 0.5 2.5 3.025 V
Input resistance 100 MΩ
Input capacitance 5 pF
Reference input current 1 μA
SERIAL CLOCK INPUT (SCLK)
Serial clock input frequency fSCLK 0.1 36 MHz
Serial clock period tSCLK 0.0278 10 μs
Serial clock duty cycle 40% 60%
DIGITAL INPUTS(4)
Logic family CMOS with Schmitt-Trigger
High-level input voltage 0.7 × BVDD BVDD + 0.3 V
Low-level input voltage BGND – 0.3 0.3 × BVDD V
Input current VI = BVDD to BGND –50 50 nA
Input capacitance 5 pF
DIGITAL OUTPUTS(4)
Logic family CMOS
High-level output voltage IOH = 100 μA BVDD – 0.6 BVDD V
Low-level output voltage IOH = –100 μA BGND BGND + 0.4 V
High-impedance-state output current –50 50 nA
Output capacitance 5 pF
Load capacitance 30 pF
POWER-SUPPLY REQUIREMENTS
Analog supply voltage AVDD 4.5 5 5.5 V
Buffer I/O supply voltage BVDD 2.7 3 5.5 V
Input positive supply voltage HVDD 5 10 16.5 V
Input negative supply voltage HVSS –16.5 –10 –5 V
Analog supply current(5) IAVDD fDATA = maximum 30 36 mA
fDATA = 250 kSPS (auto-NAP mode) 14 16.5
Auto-NAP mode, no ongoing conversion,
internal conversion clock		 4 6
Power-down mode 0.1 50 μA
Buffer I/O supply current(6) IBVDD fDATA = maximum 0.9 2 mA
fDATA = 250 kSPS (auto-NAP mode) 0.5 1.5
Auto-NAP mode, no ongoing conversion,
internal conversion clock		 0.1 10 μA
Power-down mode 0.1 10
Input positive supply current(7) IHVDD fDATA = maximum 3 3.5 mA
fDATA = 250 kSPS (auto-NAP mode) 1.6 2
Auto-NAP mode, no ongoing conversion,
internal conversion clock		 0.2 0.3 μA
Power-down mode 0.1 10
Input negative supply current(8) IHVSS fDATA = maximum 3.6 4 mA
fDATA = 250 kSPS (auto-NAP mode) 1.8 2.2
Auto-NAP mode, no ongoing conversion,
internal conversion clock		 0.2 0.25 μA
Power-down mode 0.1 10
Power dissipation(9) fDATA = maximum 251.7 298.5 mW
fDATA = 250 kSPS (auto-NAP mode) 122.5 150
Auto-NAP mode, no ongoing conversion,
internal conversion clock		 26 38.3
Power-down mode 3.8 580 μW
(1) All values are at TA = 25°C.
(2) Calculated on the first nine harmonics of the input frequency.
(3) Reference output current is not limited internally.
(4) Specified by design.
(5) At AVDD = 5 V.
(6) At BVDD = 3 V, parallel mode, load capacitance = 6 pF per pin.
(7) At HVDD = 15 V.
(8) At HVSS = –15 V.
(9) At AVDD = 5 V, BVDD = 3 V, HVDD = 15 V, and HVSS = –15 V.

6.6 Serial Interface Timing Requirements

over recommended operating free-air temperature range at –40°C to 125°C, AVDD = 5 V, and BVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN MAX UNIT
tACQ Acquisition time 280 ns
tCONV Conversion time 1.26 µs
t1 CONVST_x low time 20 ns
t2 BUSY low to FS low time 0 ns
t3 Bus access finished to next conversion start time 40 ns
tD1 CONVST_x high to BUSY high delay 5 20 ns
tD2 FS low to SDO_x active delay 5 12 ns
tD3 SCLK rising edge to new data valid delay 15 ns
tD4 FS high to SDO_x 3-state delay 10 ns
tH1 Input data to SCLK falling edge hold time 5 ns
tH2 Output data to SCLK rising edge hold time 5 ns
tS1 Input data to SCLK falling edge setup time 3 ns
tS3 CONVST_x high to XCLK falling or rising edge setup time 6 ns
tSCLK Serial clock period 0.0278 10 μs
(1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH) / 2.

6.7 Parallel Interface Timing Requirements (Read Access)

over recommended operating free-air temperature range at –40°C to 125°C, AVDD = 5 V, and BVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN MAX UNIT
tACQ Acquisition time 280 ns
tCONV Conversion time 1.26 µs
t1 CONVST_x low time 20 ns
t2 BUSY low to CS low time 0 ns
t3 Bus access finished to next conversion start time(2) 40 ns
t4 CS low to RD low time 0 ns
t5 RD high to CS high time 0 ns
t6 RD pulse width 30 ns
t7 Minimum time between two read accesses 10 ns
tD1 CONVST_x high to BUSY high delay 5 20 ns
tD5 RD falling edge to output data valid delay 20 ns
tH3 Output data to RD rising edge hold time 5 ns
(1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH) / 2.
(2) Refer to the CS signal or RD, whichever occurs first.

6.8 Parallel Interface Timing Requirements (Write Access)

over recommended operating free-air temperature range at –40°C to 125°C, AVDD = 5 V, and BVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)
MIN MAX UNIT
t8 CS low to WR low time 0 ns
t9 WR low pulse duration 15 ns
t10 WR high pulse duration 10 ns
t11 WR high to CS high time 0 ns
tS2 Output data to WR rising edge setup time 5 ns
tH4 Data output to WR rising edge hold time 5 ns
(1) All input signals are specified with tR = tF = 1.5 ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH) / 2.
ADS8555 tim_serial_bas531.gif Figure 1. Serial Operation Timing Diagram (All Three SDOs Active)
ADS8555 tim_par_rd_bas531.gif Figure 2. Parallel Read Access Timing Diagram
ADS8555 tim_par_wr_bas404.gif Figure 3. Parallel Write Access Timing Diagram

6.9 Typical Characteristics

at 25°C, over entire supply voltage range, VREF = 2.5 V (internal), and fDATA = maximum (unless otherwise noted)
ADS8555 tc_inl_8556_10vin_bas404.gif
Figure 4. INL vs Code (±10-VIN Range)
ADS8555 tc_dnl_8556_10vin_bas404.gif
Figure 6. DNL vs Code (±10-VIN Range)
ADS8555 tc_oerr-tmp_bas404.gif
Figure 8. Offset Error vs Temperature
ADS8555 tc_psrr-avdd_bas404.gif
Figure 10. PSRR vs AVDD Noise Frequency
ADS8555 tc_histo_code_bas404.gif
Figure 12. Code Histogram (8192 Hits)
ADS8555 tc_sinad-tmp_bas531.gif
Figure 14. SINAD vs Temperature
ADS8555 tc_sfdr-tmp_bas531.gif
Figure 16. SFDR vs Temperature
ADS8555 tc_fft_5vin_bas404.gif
fIN = 10 kHz
Figure 18. Frequency Spectrum
(2048-Point FFT, ±5-VIN Range)
ADS8555 tc_vref-avdd_bas404.gif
Figure 20. Internal Reference Voltage vs Analog Supply Voltage (2.5-V Mode)
ADS8555 tc_ref-tmp_3v_bas404.gif
Figure 22. Internal Reference Voltage vs Temperature
(3-V Mode)
ADS8555 tc_iavdd-dr_bas404.gif
Figure 24. Analog Supply Current vs Data Rate
ADS8555 tc_curr-tmp_bas404.gif
Figure 26. Input Supply Current vs Temperature
ADS8555 tc_in_cur-dr_bas404.gif
Figure 28. Input Supply Current vs Data Rate
ADS8555 tc_inl_8556_5vin_bas404.gif
Figure 5. INL vs Code (±5-VIN Range)
ADS8555 tc_dnl_8556_5vin_bas404.gif
Figure 7. DNL vs Code (±5-VIN Range)
ADS8555 tc_gerr-tmp_bas404.gif
Figure 9. Gain Error vs Temperature
ADS8555 tc_tconv-tmp_bas531.gif
Figure 11. Conversion Time vs Temperature
ADS8555 tc_snr-tmp_bas531.gif
Figure 13. SNR vs Temperature
ADS8555 tc_thd-tmp_bas531.gif
Figure 15. THD vs Temperature
ADS8555 tc_fft_10vin_bas404.gif
fIN = 10 kHz
Figure 17. Frequency Spectrum
(2048-Point FFT, ±10-VIN Range)
ADS8555 tc_ch2ch-noise_bas404.gif
Figure 19. Channel-to-Channel Isolation vs
Input Noise Frequency
ADS8555 tc_ref-tmp_25v_bas404.gif
Figure 21. Internal Reference Voltage vs Temperature
(2.5-V Mode)
ADS8555 tc_iavdd-tmp_bas404.gif
Figure 23. Analog Supply Current vs Temperature
ADS8555 tc_ibvdd-tmp_bas404.gif
Figure 25. Buffer I/O Supply Current vs Temperature
ADS8555 tc_curr-v_bas404.gif
Figure 27. Input Supply Current vs Input Supply Voltage
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