7.3.1.1 Analog Inputs

The inputs and the converters are of single-ended, bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the control register (CR) to either ±4 V_REF or ±2 V_REF. With the reference set to 2.5 V (CR bit C18 = 0), the input voltage range can be ±10 V or ±5 V. With the reference source set to 3 V (CR bit C18 = 1), an input voltage range of ±12 V or ±6 V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CR bit C20 = 0).

The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (t_ACQ). The source of the analog input voltage must be able to charge the input capacitance of 10 pF in ±4-V_REF mode or 20 pF in ±2-V_REF to a 12-, 14-, 16-bit accuracy level within the acquisition time of 280 ns at maximum data rate; see Figure 1. During the conversion period, there is no further input current flow and the input impedance is greater than 1 MΩ. To ensure a defined start condition, the sampling capacitors of the ADS855x are pre-charged to a fixed internal voltage before switching into sampling mode.

To maintain the linearity of the converter, the inputs must always remain within the specified range of HVSS – 0.2 V to HVDD + 0.2 V.

The minimum –3-dB bandwidth of the driving operational amplifier can be calculated using Equation 1:

Equation 1.

where

• n = 16, 14, or 12; n is the resolution of the ADS855x

With a minimum acquisition time of t_ACQ = 280 ns, the required minimum bandwidth of the driving amplifier is 6.7 MHz for the ADS8556, 6 MHz for the ADS8557, or 5.2 MHz for the ADS8558. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the bandwidth requirement shown in Equation 1.

A driving operational amplifier may not be required if the impedance of the signal source (R_SOURCE) fulfills the requirement of Equation 2:

Equation 2.

where

• n = 16, 14, or 12; n is the resolution of the ADC
• C_S = 10 pF is the sample capacitor value for V_IN = ±4 × V_REF mode
• R_SER = 200 Ω is the input resistor value
• R_SW = 130 Ω is the switch resistance value

With t_ACQ = 280 ns, the maximum source impedance must be less than 2.0 kΩ for the ADS8556, 2.3 kΩ for the ADS8557, and 2.7 kΩ for the ADS8558 in V_IN = ±4 V_REF mode or less than 0.8 kΩ for the ADS8556, 1.0 kΩ for the ADS8557, and 1.2 kΩ for the ADS8558 in V_IN = ±2 V_REF mode. The source impedance can be higher if the application allows longer acquisition time.

7.3.1.2 Analog-to-Digital Converter (ADC)

The devices include six ADCs that operate with either an internal or an external conversion clock. The conversion time can be as low as 1.09 μs with an internal conversion clock (ADS8558). When an external clock and reference are used, the minimum conversion time is 925 ns.

7.3.1.3 Conversion Clock

The device uses either an internally-generated or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. When the CLKSEL bit is set high (bit C11 in the CR), an external conversion clock of up to 20 MHz (max) can be applied on pin 27. In both cases, 18.5 clock cycles are required for a complete conversion including the pre-charging of the sample capacitors. The external clock can remain low between conversions.

The conversion clock duty cycle must be 50%. However, the ADS855x functions properly with a duty cycle between 45% and 55%.

7.3.1.4 CONVST_x

The analog inputs of each channel pair (CH_x0, CH_x1) are held with the rising edge of the corresponding CONVST_x signal. Only in software mode (except for sequential mode) is CONVST_A used for all six ADCs. The conversion automatically starts with the next edge of the conversion clock. CONVST_x must remain high during the entire conversion cycle and the BUSY signal must remain active. A falling edge during an ongoing conversion puts the related ADC pair into partial power-down mode, see the Reset and Power-Down Modes section for more details.

For simultaneous sampling, connecting all associated CONVST_x pins together is recommended. If the CONVST_x signals are not tied together, a maximum skew of 4 ns must be ensured for all three signals in any order. A CONVST_x signal issued during an ongoing conversion on any channel is blocked, except in sequential mode; see the Sequential Mode section for more details.

If a parallel interface is used, the behavior of the output port depends on which CONVST_x signals are issued. Figure 36 shows examples of different scenarios.

NOTE:

Boxed areas indicate the minimum required frame to acquire all data.

Figure 36. Data Output versus CONVST_x

7.3.1.5 BUSY/INT

The BUSY signal indicates if a conversion is in progress. The BUSY signal goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective output register. The readout of the data can be initiated immediately after the falling edge of BUSY. A falling edge of a CONVST_x input during an ongoing conversion (when BUSY is high) powers down the corresponding ADC pair.

In sequential mode, the BUSY signal goes low only for one clock cycle; see the Sequential Mode section for more details.

The polarity of the BUSY/INT signal can be changed using CR bit C20.

7.3.1.6 Reference

The ADS855x provides an internal, low-drift, 2.5-V reference source. To increase the input voltage range, the reference voltage can be switched to 3-V mode using the V_REF bit (bit C18 in the CR). The reference feeds a 10-bit string-DAC controlled by bits C[9:0] in the control register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44-mV (2.92 mV in 3-V mode) steps and adjustable to the application needs without additional external components. The actual output voltage can be calculated using Equation 3:

Equation 3.

where

• Range = the chosen maximum reference voltage output range (2.5 V or 3 V)
• Code = the decimal value of the DAC register content

Table 1 lists some examples of internal reference DAC settings with a reference range set to 2.5 V. However, to ensure proper performance, the DAC output voltage must not be programmed below 0.5 V.

Decouple the buffered output of the DAC with a 100-nF capacitor (minimum); for best performance, a 470-nF capacitor is recommended. If the internal reference is placed into power-down (default), an external reference voltage can drive the REFIO pin.

The voltage at the REFIO pin is buffered with three internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10-μF capacitor between pin pairs 53 and 54, 55 and 56, and 57 and 58. The 10-μF capacitors are available as ceramic 0805-SMD components and in X5R quality.

The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to REFC_A, REFC_B, and REFC_C pins. With 10-μF decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4:

Equation 4.

With the minimum t_CONV of 1.09 μs, the external reference buffers require a minimum bandwidth of 102 kHz.

7.3.2.1 Device Configuration

Depending on the desired mode of operation, the ADS855x can be configured using the external pins or the control register (CR), as shown in Table 2.

7.3.2.2 Parallel Interface

To use the device with the parallel interface, hold the PAR/SER pin low. The maximum achievable data throughput rate using the internal clock is 630 kSPS for the ADS8556, 670 kSPS for the ADS8557, and 730 kSPS for the ADS8558 in this case.

Access to the ADS855x is controlled as illustrated in Figure 3 and Figure 4.

The device can either operate with a 16-bit (WORD/BYTE pin set low) or an 8-bit (WORD/BYTE pin set high) parallel interface. If 8-bit operation is used, the HB_EN pin selects if the low-byte (DB7 low) or the high-byte (DB7 high) is available on the data output DB[15:8] first.

7.3.2.3 Serial Interface

The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A, SDO_B, and SDO_C depending on the selections made using the SEL_x pins. Starting with the most significant bit (MSB), the output data are changed at the rising edge of SCLK so that the host processor can read it at the following falling edge. Output data of the ADS8557 and ADS8558 maintain the 16-bit format with leading zeros.

Serial data input SDI are latched at the falling edge of SCLK.

The serial interface can be used with one, two, or three output ports. These ports are enabled with pins SEL_A, SEL_B, and SEL_C. If all three serial data output ports (SDO_A, SDO_B, and SDO_C) are selected, the data can be read with either two 16-bit data transfers or with one 32-bit data transfer. The data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 450 kSPS for the ADS8556, 470 kSPS for the ADS8557, and 500 kSPS for the ADS8558 in this case.

If the application allows a data transfer using two ports only, then the SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1 and CH_C0 on SDO_A and data from channel CH_B0 followed by CH_B1 and CH_C1 occurs on SDO_B. In this case, a data transfer of three consecutive 16-bit words or one continuous 48-bit word is supported. The maximum achievable data throughput rate is 375 kSPS for the ADS8556, 390 kSPS for the ADS8557, and 400 kSPS for the ADS8558.

The output SDO_A is selected if only one serial data port is used in the application. Data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, and, finally CH_C1. Data can be read using six 16-bit transfers, three 32-bit transfers, or a single 96-bit transfer. The maximum achievable data throughput rate is 250 kSPS for the ADS8556, ADS8557 and 260 kSPS for the ADS8558 in this case.

Figure 2 (the serial operation timing diagram) and Figure 37 illustrate all possible scenarios in more detail.

Figure 37. Serial Interface: Data Output with One or Two Active SDOs

7.3.2.4 Output Data Format

The data output format of the ADS855x is binary twos complement, as shown in Table 3.

For the ADS8557, which delivers 14-bit conversion results, the leading two bits of the 16-bit frame are '0' in the serial interface mode. In parallel interface mode, the output pins DB[15:14] are held low.

Respectively, when the ADS8558 outputs 12 bits of data, the first four bits of a serial 16-bit frame are zeros, in parallel interface mode the output pins DB[15:12] are held low.

Table 4. Maximum Analog Current (I_AVDD) Demand of the ADS855x

Table 5. Control Register (CR)