ZHCSG82 April   2017 ADS8578S

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Family Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: CONVST Control
    7. 7.7  Timing Requirements: Data Read Operation
    8. 7.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 7.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 7.10 Timing Requirements: Serial Data Read Operation
    11. 7.11 Timing Requirements: Byte Mode Data Read Operation
    12. 7.12 Timing Requirements: Oversampling Mode
    13. 7.13 Timing Requirements: Exit Standby Mode
    14. 7.14 Timing Requirements: Exit Shutdown Mode
    15. 7.15 Switching Characteristics: CONVST Control
    16. 7.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 7.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 7.18 Switching Characteristics: Serial Data Read Operation
    19. 7.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 7.20 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 Analog Input Impedance
      3. 8.3.3 Input Clamp Protection Circuit
      4. 8.3.4 Programmable Gain Amplifier (PGA)
      5. 8.3.5 Third-Order, Low-Pass Filter (LPF)
      6. 8.3.6 ADC Driver
      7. 8.3.7 Digital Filter and Noise
      8. 8.3.8 Reference
        1. 8.3.8.1 Internal Reference
        2. 8.3.8.2 External Reference
        3. 8.3.8.3 Supplying One VREF to Multiple Devices
      9. 8.3.9 ADC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Interface: Pin Description
        1. 8.4.1.1  REFSEL (Input)
        2. 8.4.1.2  RANGE (Input)
        3. 8.4.1.3  STBY (Input)
        4. 8.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 8.4.1.5  CONVSTA, CONVSTB (Input)
        6. 8.4.1.6  RESET (Input)
        7. 8.4.1.7  RD/SCLK (Input)
        8. 8.4.1.8  CS (Input)
        9. 8.4.1.9  OS[2:0]
        10. 8.4.1.10 BUSY (Output)
        11. 8.4.1.11 FRSTDATA (Output)
        12. 8.4.1.12 DB15/BYTE SEL
        13. 8.4.1.13 DB14/HBEN
        14. 8.4.1.14 DB[13:9]
        15. 8.4.1.15 DB8/DOUTB
        16. 8.4.1.16 DB7/DOUTA
        17. 8.4.1.17 DB[6:0]
      2. 8.4.2 Device Modes of Operation
        1. 8.4.2.1 Power-Down Modes
          1. 8.4.2.1.1 Standby Mode
          2. 8.4.2.1.2 Shutdown Mode
        2. 8.4.2.2 Conversion Control
          1. 8.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 8.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 8.4.2.3 Data Read Operation
          1. 8.4.2.3.1 Parallel Data Read
          2. 8.4.2.3.2 Parallel Byte Data Read
          3. 8.4.2.3.3 Serial Data Read
          4. 8.4.2.3.4 Data Read During Conversion
        4. 8.4.2.4 Oversampling Mode of Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

PM Package
64-Pin LQFP
Top View
ADS8578S po_sbas825.gif

Pin Functions

NAME NO. TYPE(1) DESCRIPTION
AGND 2, 26, 35, 40, 41, 47 P Analog ground pins
AIN_1GND 50 AI Analog input channel 1: negative input
AIN_1P 49 AI Analog input channel 1: positive input
AIN_2GND 52 AI Analog input channel 2: negative input
AIN_2P 51 AI Analog input channel 2: positive input
AIN_3GND 54 AI Analog input channel 3: negative input
AIN_3P 53 AI Analog input channel 3: positive input
AIN_4GND 56 AI Analog input channel 4: negative input
AIN_4P 55 AI Analog input channel 4: positive input
AIN_5GND 58 AI Analog input channel 5: negative input
AIN_5P 57 AI Analog input channel 5: positive input
AIN_6GND 60 AI Analog input channel 6: negative input
AIN_6P 59 AI Analog input channel 6: positive input
AIN_7GND 62 AI Analog input channel 7: negative input
AIN_7P 61 AI Analog input channel 7: positive input
AIN_8GND 64 AI Analog input channel 8: negative input
AIN_8P 63 AI Analog input channel 8: positive input
AVDD 1, 37, 38, 48 P Analog supply pins. Decouple these pins to the closest AGND pins
(see the Power Supply Recommendations section).
BUSY 14 DO Active high digital output indicating an ongoing conversion
(see the BUSY (Output) section)
CONVSTA 9 DI Active high logic input to control start of conversion for first half count of device input channels (see the CONVSTA, CONVSTB (Input) section)
CONVSTB 10 DI Active high logic input to control start of conversion for second half count of device input channels (see the CONVSTA, CONVSTB (Input) section)
CS 13 DI Active low logic input chip-select signal (see the CS (Input) section)
DB0 16 DO DB0 is driven low in parallel interface mode; in parallel byte interface mode, DB0 is ADC data output bit 6 and is driven low (see the DB[6:0] section)
DB1 17 DO Driven low in parallel interface mode; in parallel byte interface mode, DB1 is ADC data output bit 7 and is driven low (see the DB[6:0] section)
DB2 18 DO ADC data output bit 0 in parallel interface mode; in parallel byte interface mode, DB2 is ADC data output bits 8 and 0 and is driven low (see the DB[6:0] section)
DB3 19 DO ADC data output bit 1 in parallel interface mode; in parallel byte interface mode, DB3 is ADC data output bits 9 and 1 and is driven low (see the DB[6:0] section)
DB4 20 DO ADC data output bit 2 in parallel interface mode; in parallel byte interface mode, DB4 is ADC data output bits 10 and 2 and is driven low (see the DB[6:0] section)
DB5 21 DO ADC data output bit 3 in parallel interface mode; in parallel byte interface mode, DB5 is ADC data output bits 11 and 3 and is driven low (see the DB[6:0] section)
DB6 22 DO ADC data output bit 4 in parallel interface mode; in parallel byte interface mode, DB6 is ADC data output bits 12 and 4 and is driven low (see the DB[6:0] section)
DB7/DOUTA 24 DO Multifunction logic output pin (see the DB7/DOUTA section):
this pin is ADC data output bit 5 in parallel interface mode, ADC data output bits 13 and 5 in parallel byte interface mode, and is a data output pin in serial interface mode.
DB8/DOUTB 25 DO Multifunction logic output pin (see the DB8/DOUTB section):
this pin is ADC data output bit 6 in parallel interface mode and is a data output pin in serial interface mode.
DB9 27 DO ADC data output bit 7 in parallel interface mode (see the DB[13:9] section)
DB10 28 DO ADC data output bit 8 in parallel interface mode (see the DB[13:9] section)
DB11 29 DO ADC data output bit 9 in parallel interface mode (see the DB[13:9] section)
DB12 30 DO ADC data output bit 10 in parallel interface mode (see the DB[13:9] section)
DB13 31 DO ADC data output bit 11 in parallel interface mode (see the DB[13:9] section)
DB14/HBEN 32 DIO Multifunction logic input or output pin (see the DB14/HBEN section):
this pin is ADC data output bit 12 in parallel interface mode, and is a control input pin for byte selection (high or low) in parallel byte interface mode.
DB15/BYTE SEL 33 DIO Multifunction logic input or output pin (see the DB15/BYTE SEL section):
this pin is ADC data output bit 13 (MSB) in parallel interface mode, and is an active high control input pin to enable parallel byte interface mode.
DVDD 23 P Digital supply pin; decouple with AGND on pin 26
FRSTDATA 15 DO Active high digital output indicating data read back from channel 1 of the device (see the FRSTDATA (Output) section)
OS0 3 DI Oversampling mode control pin (see the Oversampling Mode of Operation section)
OS1 4 DI Oversampling mode control pin (see the Oversampling Mode of Operation section)
OS2 5 DI Oversampling mode control pin (see the Oversampling Mode of Operation section)
PAR/SER/BYTE SEL 6 DI Logic input pin to select between parallel, serial, or parallel byte interface mode (see the Data Read Operation section)
RANGE 8 DI Multifunction logic input pin (see the RANGE (Input) section):
when the STBY pin is high, this pin selects the input range of the device (±10 V or ±5 V); when the STBY pin is low, this pin selects between the standby and shutdown modes.
RD/SCLK 12 DI Multifunction logic input pin (see the RD/SCLK (Input) section):
this pin is an active-low ready input pin in parallel and parallel byte interface, and is a clock input pin in serial interface mode.
REFCAPA 44 AO Reference amplifier output pin. This pin must be shorted to REFCAPB and decoupled to AGND using a low equivalent series resistance (ESR), 10-µF ceramic capacitor.
REFCAPB 45 AO Reference amplifier output pin. This pin must be shorted to REFCAPA and decoupled to AGND using a low ESR, 10-µF ceramic capacitor.
REFGND 43, 46 P Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with REFIN/REFOUT on pin 42 using a 10-µF capacitor.
REFIN/REFOUT 42 AIO This pin acts as an internal reference output when REFSEL is high;
this pin functions as input pin for the external reference when REFSEL is low; decouple with REFGND on pin 43 using a 10-µF capacitor.
REFSEL 34 DI Active high logic input to enable the internal reference (see the REFSEL (Input) section)
REGCAP1 36 AO Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor
REGCAP2 39 AO Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-µF capacitor
RESET 11 DI Active high logic input to reset the device digital logic (see the RESET (Input) section)
STBY 7 DI Active low logic input to enter the device into one of the two power-down modes: standby or shutdown (see the Power-Down Modes section)
(1) AI = analog input; AO = analog output; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; P = power supply; and NC = no connect.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |