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7.1 Absolute Maximum Ratings

at T_A = 25°C (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
AVDD to AGND		–0.3	7.0	V
DVDD to AGND		–0.3	7.0	V
Analog input voltage to AGND⁽²⁾		–15	15	V
Digital input to AGND		–0.3	DVDD + 0.3	V
REFIN to AGND		–0.3	AVDD + 0.3	V
Input current to any pin except supplies⁽²⁾		–10	10	mA
Temperature	Operating	–40	125	°C
	Junction, T_J		150
	Storage, T_stg	–65	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Transient currents of up to 100 mA do not cause SCR latch-up.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins except analog inputs	±2000	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	Analog input pins only	±7000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	All pins	±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
AVDD	Analog supply voltage	4.75	5	5.25	V
DVDD	Digital supply voltage	2.3	3.3	AVDD	V

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS8584S	UNIT
		PM (LQFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	46.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.8	°C/W
R_θJB	Junction-to-board thermal resistance	20.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	19.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

minimum and maximum specifications are at T_A = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at T_A = 25°C; AVDD = 5 V, DVDD = 3 V, V_REF = 2.5 V (internal), and f_SAMPLE = 330 kSPS (unless otherwise noted)

PARAMETER			TEST CONDITIONS		MIN	TYP	MAX	UNIT	TEST LEVEL⁽⁸⁾
ANALOG INPUTS
	Full-scale input span⁽¹⁾ (AIN_nP to AIN_nGND)		RANGE pin = 1		–10		10	V	A
	Full-scale input span⁽¹⁾ (AIN_nP to AIN_nGND)		RANGE pin = 0		–5		5	V	A
AIN_nP	Operating input range, positive input		RANGE pin = 1		–10		10	V	A
AIN_nP	Operating input range, positive input		RANGE pin = 0		–5		5	V	A
AIN_nGND	Operating input range, negative input		All input ranges		–0.3	0	0.3	V	B
R_IN	Input impedance		At T_A = 25°C		0.85	1	1.15	MΩ	B
	Input impedance drift		All input ranges		–25	±7	25	ppm/°C	B
I_Ikg(in)	Input leakage current		With voltage at AIN_nP = V_IN, all input ranges		(V_IN – 2) / R_IN			µA	A
SYSTEM PERFORMANCE
	Resolution				16			Bits	A
NMC	No missing codes				16			Bits	A
DNL	Differential nonlinearity		All input ranges		–0.5	±0.35	0.5	LSB⁽²⁾	A
INL	Integral nonlinearity⁽⁴⁾		All input ranges		–1.5	±0.45	1.5	LSB	A
E_G	Gain error⁽⁹⁾		All input ranges, external reference	T_A = –40°C to +85°C	–64	±4	64	LSB	A
			All input ranges, external reference	T_A = –40°C to +125°C	–64	±4	96		A
			All input ranges, internal reference			±4			A
	Gain error matching (channel-to-channel)		Input range = ±10 V, external and internal reference			10	60	LSB	A
	Gain error matching (channel-to-channel)		Input range = ±5 V, external and internal reference			12	60	LSB	A
	Gain error temperature drift		All input ranges, external reference		–14	±6	14	ppm/°C	B
	Gain error temperature drift		All input ranges, internal reference			±10		ppm/°C	B
E_O	Offset error		Input range = ±10 V		–1.8	±0.15	1.8	mV	B
E_O	Offset error		Input range = ±5 V		–1.8	±0.15	1.8	mV	B
	Offset error matching (channel-to-channel)		All input ranges			0.3	2.4	mV	B
	Offset error temperature drift		All input ranges		–3	±0.3	3	ppm/°C	B
SAMPLING DYNAMICS
t_ACQ	Acquisition time				1			µs	A
f_S	Maximum throughput rate per channel without latency		All four channels included				330	kSPS	A
DYNAMIC CHARACTERISTICS
SNR	Signal-to-noise ratio, no oversampling (V_IN – 0.5 dBFS at 1 kHz)		Input range = ±10 V		91	92.7		dB	A
SNR			Input range = ±5 V		90.4	92.2		dB	A
SNR_OSR	Signal-to-noise ratio, oversampling = 16x (V_IN – 0.5 dBFS at 130 Hz)		Input range = ±10 V		95.5	96.4		dB	A
SNR_OSR			Input range = ±5 V		94.4	95.5		dB	A
THD	Total harmonic distortion⁽³⁾ (V_IN – 0.5 dBFS at 1 kHz)		All input ranges			–114	–95	dB	B
SINAD	Signal-to-noise + distortion ratio, no oversampling (V_IN – 0.5 dBFS at 1 kHz)		Input range = ±10 V		90.7	92.7		dB	A
SINAD			Input range = ±5 V		90.2	92.1		dB	A
SINAD_OSR	Signal-to-noise + distortion ratio, oversampling = 16x (V_IN – 0.5 dBFS at 130 Hz)		Input range = ±10 V		95	96.4		dB	A
SINAD_OSR			Input range = ±5 V		94	95.4		dB	A
SFDR	Spurious-free dynamic range (V_IN – 0.5 dBFS at 1 kHz)		All input ranges			–118		dB	B
	Crosstalk isolation⁽⁵⁾					–95		dB	A
BW_{(–3 dB)}	Small-signal bandwidth	–3 dB	At T_A = 25°C, input range = ±10 V			24		kHz	B
BW_{(–3 dB)}		–3 dB	At T_A = 25°C, input range = ±5 V			16		kHz	B
BW_{(–0.1 dB)}		–0.1 dB	At T_A = 25°C, input range = ±10 V			14		kHz	B
BW_{(–0.1 dB)}		–0.1 dB	At T_A = 25°C, input range = ±5 V			9.5		kHz	B
t_GROUP	Group delay		Input range = ±10 V			13		µs	C
t_GROUP	Group delay		Input range = ±5 V			19		µs	C
INTERNAL REFERENCE OUTPUT (REFSEL = 1)
V_REF⁽⁶⁾	Voltage on the REFIN/REFOUT pin (configured as output)		At T_A = 25°C		2.4975	2.5	2.5025	V	A
	Internal reference temperature drift					7.5		ppm/°C	B
C_{(REFIN_ REFOUT)}	Decoupling capacitor on REFIN/REFOUT⁽⁷⁾					10		µF	B
V_(REFCAP)	Reference voltage to the ADC (on the REFCAPA, REFCAPB pin)		At T_A = 25°C		3.996	4.0	4.004	V	A
	Reference buffer output impedance					0.5	1	Ω	C
	Reference buffer output temperature drift					5		ppm/°C	B
C_(REFCAP)	Decoupling capacitor on REFCAPA, REFCAPB					10		µF	B
	Turn-on time		C_(REFCAP) = 10 µF, C_{(REFIN_REFOUT)} = 10 µF			25		ms	B
EXTERNAL REFERENCE INPUT (REFSEL = 0)
V_{REFIO_EXT}	External reference voltage on REFIO (configured as input)				2.475	2.5	2.525	V	B
	Reference input impedance					100		MΩ	C
	Reference input capacitance					10		pF	C
POWER-SUPPLY REQUIREMENTS
AVDD	Analog power-supply voltage		Analog supply		4.75	5	5.25	V	A
DVDD	Digital power-supply voltage		Digital supply range		2.3	3.3	AVDD	V	A
I_{AVDD_DYN}	Analog supply current (operational)		For ADS8584S, AVDD = 5 V, f_S = 330 kSPS, internal reference			10.9	14.8	mA	A
I_{AVDD_DYN}	Analog supply current (operational)		For ADS8584S, AVDD = 5 V, f_S = 330 kSPS, external reference			10.4	14.1	mA	A
I_{AVDD_STC}	Analog supply current (static)		For ADS8584S, AVDD = 5 V, internal reference, device not converting			8.0	10.9	mA	A
I_{AVDD_STC}	Analog supply current (static)		For ADS8584S, AVDD = 5 V, external reference, device not converting			7.5	10.2	mA	A
I_{AVDD_STDBY}	AVDD supply STANDBY current		At AVDD = 5 V, device in STDBY mode, internal reference			3.2	4.2	mA	A
I_{AVDD_STDBY}	AVDD supply STANDBY current		At AVDD = 5 V, device in STDBY mode, external reference			2.7	3.6	mA	A
I_{AVDD_PWR_ DN}	AVDD supply power-down current		At AVDD = 5 V, device in PWR_DN, internal or external reference, T_A = –40°C to +85°C			0.2	6	µA	A
I_{DVDD_DYN}	Digital supply current		For ADS8584S, DVDD = 3.3 V, f_S = 330 kSPS			0.15	0.3	mA	A
I_{DVDD_STDBY}	DVDD supply STANDBY current		At AVDD = 5 V, device in STDBY mode			0.05	1.5	µA	A
I_{DVDD_PWR-DN}	DVDD supply power-down current		At AVDD = 5 V, device in PWR_DN mode			0.05	1.5	µA	A
DIGITAL INPUTS (CMOS)
V_IH	Digital high input voltage logic level		DVDD > 2.3 V		0.7 × DVDD		DVDD + 0.3	V	A
V_IL	Digital low input voltage logic level		DVDD > 2.3 V		–0.3		0.3 × DVDD	V	A
	Input leakage current					100		nA	A
	Input pin capacitance					5		pF	A
DIGITAL OUTPUTS (CMOS)
V_OH	Digital high output voltage logic level		I_O = 100-µA source		0.8 × DVDD		DVDD	V	A
V_OL	Digital low output voltage logic level		I_O = 100-µA sink		0		0.2 × DVDD	V	A
	Floating state leakage current		Only for SDO			1		µA	A
	Internal pin capacitance					5		pF	A
TEMPERATURE RANGE
T_A	Operating free-air temperature				–40		125	°C	A

(1) Ideal input span, does not include gain or offset error.

(2) LSB = least significant bit.

(3) Calculated on the first nine harmonics of the input frequency.

(4) This parameter is the endpoint INL, not best-fit INL.

(5) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel.

(6) Does not include the variation in voltage resulting from solder shift effects.

(7) Recommended to use an X7R-grade, 0603-size ceramic capacitor for optimum performance (see the Layout Guidelines section).

(8) Test Levels: (A) Tested at final test. Overtemperature limits are set by characterization and simulation. (B) Limits set by characterization and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.

(9) Gain error is calculated after adjusting for offset error, which implies that positive full-scale error = negative full-scale error = gain error ÷ 2.

7.6 Timing Requirements: CONVST Control

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), BUSY load = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 1)

		MIN	MAX	UNIT
t_ACQ	Acquisition time: BUSY falling edge to rising edge of trailing CONVSTA or CONVSTB	1		µs
t_{PH_CN}	CONVSTA, CONVSTB pulse high time	25		ns
t_{PL_CN}	CONVSTA, CONVSTB pulse low time	25		ns
t_{SU_BSYCS}	Setup time: BUSY falling to CS falling	0		ns
t_{SU_RSTCN}	Setup time: RESET falling to first rising edge of CONVSTA or CONVSTB	25		ns
t_{PH_RST}	RESET pulse high time	50		ns
t_{D_CNAB}	Delay between rising edges of CONVSTA and CONVSTB		500	µs

7.7 Timing Requirements: Data Read Operation

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), BUSY load = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 2)

		MIN	UNIT
t_{DZ_CNCS}	Delay between CONVSTA, CONVSTB rising edge to CS falling edge, start of data read operation during conversion	10	ns
t_{DZ_CSBSY}	Delay between CS rising edge to BUSY falling edge, end of data read operation during conversion	40	ns
t_{SU_BSYCS}	Setup time: BUSY falling edge to CS falling edge, start of data read operation after conversion	0	ns
t_{D_CSCN}	Delay between CS rising edge to CONVSTA, CONVSTB rising edge, end of data read operation after conversion	10	ns

7.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 3)

		MIN	UNIT
t_{PH_CS}, t_{PH_RD}	CS and RD high time	15	ns
t_{PL_CS}, t_{PL_RD}	CS and RD low time	15	ns
t_{HT_RDDB}, t_{HT_CSDB}	Hold time: RD and CS rising edge to DB[15:0] invalid	2.5	ns

7.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 4)

		MIN	UNIT
t_{SU_CSRD}	Setup time: CS falling edge to RD falling edge	0	ns
t_{HT_RDCS}	Hold time: RD rising edge to CS rising edge	0	ns
t_{PL_RD}	RD low time	15	ns
t_{PH_RD}	RD high time	15	ns
t_{HT_CSDB}	Hold time: CS rising edge to DB[15:0] becoming invalid	6	ns
t_{HT_RDDB}	Hold time: RD rising edge to DB[15:0] becoming invalid	2.5	ns

7.10 Timing Requirements: Serial Data Read Operation

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 5)

		MIN	MAX	UNIT
t_SCLK	SCLK time period	50		ns
t_{PH_SCLK}	SCLK high time	0.45	0.55	t_SCLK
t_{PL_SCLK}	SCLK low time	0.45	0.55	t_SCLK
t_{HT_CKDO}	Hold time: SCLK rising edge to DOUTA, DOUTB invalid	7		ns
t_{SU_CSCK}	Setup time: CS falling to first SCLK edge	8		ns
t_{HT_CKCS}	Hold time: last SCLK active edge to CS high	10		ns

7.11 Timing Requirements: Byte Mode Data Read Operation

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 6)

		MIN	UNIT
t_{SU_CSRD}	Setup time: CS falling edge to RD falling edge	0	ns
t_{HT_RDCS}	Hold time: RD rising edge to CS rising edge	0	ns
t_{PL_RD}	RD low time	15	ns
t_{PH_RD}	RD high time	15	ns
t_{HT_CSDB}	Hold time: CS rising edge to DB[15:0] becoming invalid	6	ns
t_{HT_RDDB}	Hold time: RD rising edge to DB[15:0] becoming invalid	2.5	ns

7.12 Timing Requirements: Oversampling Mode

		MIN	NOM	MAX	UNIT
t_{HT_OS}	Hold time: BUSY falling to OSx	20			ns
t_{SU_OS}	Setup time: BUSY falling to OSx	20			ns

7.13 Timing Requirements: Exit Standby Mode

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C, AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 8)

		MIN	NOM	MAX	UNIT
t_{D_STBYCN}	Delay between STBY rising edge to CONVSTA or CONVSTB rising edge⁽¹⁾	100			µs

(1) First conversion data must be discarded or RESET must be issued if the maximum timing is exceeded.

7.14 Timing Requirements: Exit Shutdown Mode

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 9)

			MIN	UNIT
t_{D_SDRST}	Delay between STBY rising edge to RESET rising edge	Internal reference mode	50	ms
t_{D_SDRST}	Delay between STBY rising edge to RESET rising edge	External reference mode⁽¹⁾	13	ms
t_{PH_RST}	RESET high time		50	ns
t_{D_RSTCN}	Delay between RESET falling edge to CONVSTA or CONVSTB rising edge		25	µs

(1) Excludes wake-up time for external reference device.

7.15 Switching Characteristics: CONVST Control

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), BUSY load = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 1)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_CYC	ADC cycle time period	No oversampling, parallel read, serial read with both DOUTA and DOUTB during conversion	3			µs
		No oversampling, serial read after conversion with both DOUTA and DOUTB	3.8
		No oversampling, serial read after conversion with only DOUTA or DOUTB	5.5
t_CONV	Conversion time: BUSY high time	No oversampling		2		µs
		Oversampling by 2		5
		Oversampling by 4		11
		Oversampling by 8		23
		Oversampling by 16		47
		Oversampling by 32		95
		Oversampling by 64		191
t_{D_CNBSY}	Delay between trailing rising edges of CONVSTA or CONVSTB and BUSY rising				15	ns

7.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 3)

PARAMETER		MAX	UNIT
t_{D_CSDB}	Delay time: CS falling edge to DB[15:0] becoming valid (out of tri-state)	12	ns
t_{D_RDDB}	Delay time: RD falling edge to new data on DB[15:0]	17	ns
t_{D_CSFD}, t_{D_RDFD}	Delay time: CS and RD falling edge to FRSTDATA going high or low out of tri-state	10	ns
t_{DHZ_CSDB}, t_{DHZ_RDDB}	Delay time: CS and RD rising edge to DB[15:0] tri-state	12	ns
t_{DHZ_CSFD}, t_{DHZ_RDFD}	Delay time: CS and RD rising edge to FRSTDATA tri-state	10	ns

7.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DB[15:0] and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 4)

PARAMETER		MAX	UNIT
t_{D_CSDB}	Delay time: CS falling edge to DB[15:0] becoming valid (out of tri-state)	12	ns
t_{D_RDDB}	Delay time: RD falling edge to new data on DB[15:0]	17	ns
t_{DHZ_CSDB}	Delay time: CS rising edge to DB[15:0] becoming tri-state	12	ns
t_{D_CSFD}	Delay time: CS falling edge to FRSTDATA going low out of tri-state	15	ns
t_{DHZ_CSFD}	Delay time: CS rising edge to FRSTDATA going to tri-state	10	ns
t_{D_RDFD}	Delay time: RD falling edge to FRSTDATA going high or low	15	ns

7.18 Switching Characteristics: Serial Data Read Operation

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DOUTA, DOUTB, and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 5)

PARAMETER		MAX	UNIT
t_{D_CSDO}	Delay time: CS falling edge to DOUTA, DOUTB enable (out of tri-state)	12	ns
t_{D_CKDO}	Delay time: SCLK rising edge to valid data on DOUTA, DOUTB	15	ns
t_{DZ_CSDO}	Delay time: CS rising edge to DOUTA, DOUTB going to tri-state	12	ns
t_{D_CSFD}	Delay time: CS falling edge to FRSTDATA from tri-state to high or low	10	ns
t_{DZ_CKFD}	Delay time: 16th SCLK falling edge to FRSTDATA falling edge	15	ns
t_{DHZ_CSFD}	Delay time: CS rising edge to FRSTDATA going to tri-state	10	ns

7.19 Switching Characteristics: Byte Mode Data Read Operation

minimum and maximum specifications are at T_A = –40°C to +125°C, typical specifications are at T_A = 25°C; AVDD = 5 V, 2.3 V ≤ DVDD ≤ 5.25 V, V_REF = 2.5 V (internal), load on DB[7:0] and FRSTDATA = 20 pF, V_IL and V_IH at datasheet limits, and f_SAMPLE = 330 kSPS (unless otherwise noted) (see Figure 6)

PARAMETER		MAX	UNIT
t_{D_CSDB}	Delay time: CS falling edge to DB[7:0] becoming valid (out of tri-state)	12	ns
t_{D_RDDB}	Delay time: RD falling edge to new data on DB[7:0]	17	ns
t_{DHZ_CSDB}	Delay time: CS rising edge to DB[7:0] becoming tri-state	12	ns
t_{D_CSFD}	Delay time: CS falling edge to FRSTDATA going low out of tri-state	10	ns
t_{D_RDFD}	Delay time: RD falling edge to FRSTDATA going low or high state	15	ns
t_{DHZ_CSFD}	Delay time: CS rising edge to FRSTDATA going to tri-state	10	ns

7.20 Typical Characteristics

at T_A = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF = 2.5 V, and f_S = 330 kSPS per channel (unless otherwise noted)

Figure 10. Analog Input Current vs Input Voltage Over Temperature (±10 V)

Figure 12. Input Impedance vs Temperature

Mean = –0.02, sigma = 0.54, number of hits = 4096, V_IN = 0 V

Figure 14. DC Histogram of Codes (±5 V)

Figure 16. DNL vs Temperature

Figure 18. INL vs All Codes (±5 V)

Figure 20. INL vs Temperature (±5 V)

Figure 22. Offset Drift Histogram Distribution (±10 V)

Figure 24. Offset Drift Histogram Distribution (±5 V)

External reference

Figure 26. Gain Error vs Temperature

External reference

Figure 28. Gain Error Across Channels vs Temperature
(±10 V)

External reference

Figure 30. Gain Error Across Channels vs Temperature
(±5 V)

Number of points = 32k, SNR = 92.61 dB,
SINAD = 92.53 dB, THD = –110.64 dB, SFDR = 113.89 dB

Figure 32. Typical FFT Plot (±10 V)

Number of points = 32k, SNR = 96.31 dB,
SINAD = 95.9 dB, THD = –111.23 dB, SFDR = 115.01 dB

Figure 34. Typical FFT Plot for OSR 16x (±10 V)

OSR = 0

Figure 36. SNR vs Input Frequency for Different Input Ranges

Figure 38. SNR vs Input Frequency for Different OSR
(±10 V)

OSR = 0

Figure 40. SINAD vs Input Frequency for Different Input Ranges

Figure 42. THD vs Input Frequency for Different Input Ranges

Figure 44. THD vs Input Frequency for Different Source Impedances (±10 V)

Figure 46. Isolation Crosstalk vs Noise Frequency
(Inputs Within Range)

Figure 48. Analog Supply Current (Operational) vs Temperature

Figure 50. Analog Supply Current vs Temperature
(Standby)

Figure 11. Analog Input Current vs Input Voltage Over Temperature (±5 V)

Mean = –0.14, sigma = 0.51, number of hits = 4096, V_IN = 0 V

Figure 13. DC Histogram of Codes (±10 V)

Figure 15. DNL for All Codes

Figure 17. INL vs All Codes (±10 V)

Figure 19. INL vs Temperature (±10 V)

Figure 21. Offset Error vs Temperature

Figure 23. Offset Error Across Channels vs Temperature
(±10 V)

Figure 25. Offset Error Across Channels vs Temperature
(±5 V)

External reference

Figure 27. Gain Error Drift Histogram Distribution (±10 V)

External reference

Figure 29. Gain Error Drift Histogram Distribution (±5 V)

Figure 31. Gain Error as a Function of External Source Resistance

Number of points = 32k, SNR = 92.25 dB,
SINAD = 92.12 dB, THD = –110.78 dB, SFDR = 114.02 dB

Figure 33. Typical FFT Plot (±5 V)

Number of points = 32k, SNR = 95.54 dB,
SINAD = 95.01 dB, THD = –110.08 dB, SFDR = 114.67 dB

Figure 35. Typical FFT Plot for OSR 16x (±5 V)

OSR = 0

Figure 37. SNR vs Temperature for Different Input Ranges

Figure 39. SNR vs Input Frequency for Different OSR
(±5 V)

OSR = 0

Figure 41. SINAD vs Temperature for Different Input Ranges

Figure 43. THD vs Temperature for Different Input Ranges

Figure 45. THD vs Input Frequency for Different Source Impedances (±5 V)

Figure 47. Isolation Crosstalk vs Noise Frequency (Saturated Inputs)

Figure 49. Analog Supply Current (Static) vs Temperature (Sampling)

Figure 51. Analog Supply Current vs Temperature (Shutdown)

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7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 Timing Requirements: CONVST Control

7.7 Timing Requirements: Data Read Operation

7.8 Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together

7.9 Timing Requirements: Parallel Data Read Operation, CS and RD Separate

7.10 Timing Requirements: Serial Data Read Operation

7.11 Timing Requirements: Byte Mode Data Read Operation

7.12 Timing Requirements: Oversampling Mode

7.13 Timing Requirements: Exit Standby Mode

7.14 Timing Requirements: Exit Shutdown Mode

7.15 Switching Characteristics: CONVST Control

7.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together

7.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate

7.18 Switching Characteristics: Serial Data Read Operation

7.19 Switching Characteristics: Byte Mode Data Read Operation

7.20 Typical Characteristics