米6体育平台手机版

ZHCSGU6A september 2017 – july 2023 ADS8588H

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PM|64
- MTQF008B

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.5 Electrical Characteristics

minimum and maximum specifications are at T_A = –40°C to +125°C, AVDD = 4.75 V to 5.25 V; typical specifications are at T_A = 25°C; AVDD = 5 V, DVDD = 3 V, V_REF = 2.5 V (internal), and f_SAMPLE = 500 kSPS (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Full-scale input span⁽¹⁾ (AIN_nP to AIN_nGND)	RANGE pin = 1		–10		10	V
	Full-scale input span⁽¹⁾ (AIN_nP to AIN_nGND)	RANGE pin = 0		–5		5	V
AIN_nP	Operating input range, positive input	RANGE pin = 1		–10		10	V
AIN_nP	Operating input range, positive input	RANGE pin = 0		–5		5	V
AIN_nGND	Operating input range, negative input	RANGE pin = 1		–0.3	0	0.3	V
AIN_nGND	Operating input range, negative input	RANGE pin = 0		–0.3	0	0.3	V
R_IN	Input impedance	At T_A = 25°C		0.85	1	1.15	MΩ
	Input impedance drift	All input ranges		–25	±7	25	ppm/°C
I_Ikg(in)	Input leakage current	With voltage at AIN_nP = V_IN, all input ranges		(V_IN – 2) / R_IN			µA
SYSTEM PERFORMANCE
	Resolution			16			Bits
NMC	No missing codes			16			Bits
DNL	Differential nonlinearity	All input ranges		–0.6	±0.3	0.6	LSB⁽²⁾
INL	Integral nonlinearity⁽⁵⁾	All input ranges		–1.5	±0.5	1.5	LSB
E_G	Gain error⁽⁹⁾	All input ranges, external reference	T_A = –40°C to +85°C	–64	±4	64	LSB
		All input ranges, external reference	T_A = –40°C to +125°C	–64	±4	96
		All input ranges, internal reference			±4
	Gain error matching (channel-to-channel)	Input range = ±10 V, external and internal reference			10	60	LSB
	Gain error matching (channel-to-channel)	Input range = ±5 V, external and internal reference			12	60	LSB
	Gain error temperature drift	All input ranges, external reference		–14	±6	14	ppm/°C
	Gain error temperature drift	All input ranges, internal reference			±10		ppm/°C
E_O	Offset error	Input range = ±10 V		–3	±0.2	3	mV
E_O	Offset error	Input range = ±5 V		–3	±0.15	3	mV
	Offset error matching (channel-to-channel)	All input ranges			0.7	5	mV
	Offset error temperature drift	All input ranges		–3	±0.3	3	ppm/°C
SAMPLING DYNAMICS
t_ACQ	Acquisition time			0.7			µs
f_S	Maximum throughput rate per channel without latency	All eight channels included				500	kSPS
DYNAMIC CHARACTERISTICS
SNR	Signal-to-noise ratio⁽³⁾, no oversampling (V_IN – 0.5 dBFS at 1 kHz)	Input range = ±10 V		91	92.7		dB
SNR		Input range = ±5 V		89.5	92.1		dB
SNR_OSR	Signal-to-noise ratio⁽³⁾, oversampling = 32x (V_IN – 0.5 dBFS at 130 Hz)	Input range = ±10 V		95.5	96.9		dB
SNR_OSR		Input range = ±5 V		94	95.8		dB
THD	Total harmonic distortion⁽³⁾⁽⁴⁾ (V_IN – 0.5 dBFS at 1 kHz)	All input ranges			–110	–95	dB
SINAD	Signal-to-noise + distortion ratio⁽³⁾, no oversampling (V_IN – 0.5 dBFS at 1 kHz)	Input range = ±10 V		90.9	92.6		dB
SINAD		Input range = ±5 V		89.2	92		dB
SINAD_OSR	Signal-to-noise + distortion ratio⁽³⁾, oversampling = 16 x (V_IN – 0.5 dBFS at 130 Hz)	Input range = ±10 V		94.75	96.5		dB
SINAD_OSR		Input range = ±5 V		93.5	95.3		dB
SFDR	Spurious-free dynamic range (V_IN – 0.5 dBFS at 1 kHz)	All input ranges			110		dB
	Crosstalk isolation⁽⁶⁾				–95		dB
BW_{(–3 dB)}	Small-signal bandwidth, –3 dB	At T_A = 25°C, input range = ±10 V			24		kHz
BW_{(–3 dB)}	Small-signal bandwidth, –3 dB	At T_A = 25°C, input range = ±5 V			16		kHz
BW_{(–0.1 dB)}	Small-signal bandwidth, –0.1 dB	At T_A = 25°C, input range = ±10 V			14		kHz
BW_{(–0.1 dB)}	Small-signal bandwidth, –0.1 dB	At T_A = 25°C, input range = ±5 V			9.5		kHz
t_GROUP	Group delay	Input range = ±10 V			13		µs
t_GROUP	Group delay	Input range = ±5 V			19		µs
INTERNAL REFERENCE OUTPUT (REFSEL = 1)
V_REF⁽⁷⁾	Voltage on the REFIN/REFOUT pin (configured as output)	At T_A = 25°C		2.4975	2.5	2.5025	V
	Internal reference temperature drift				7.5		ppm/°C
C_{(REFIN_ REFOUT)}	Decoupling capacitor on REFIN/REFOUT⁽⁸⁾				10		µF
V_(REFCAP)	Reference voltage to the ADC (on the REFCAPA, REFCAPB pin)	At T_A = 25°C		3.996	4.0	4.004	V
	Reference buffer output impedance				0.5	1	Ω
	Reference buffer output temperature drift				5		ppm/°C
C_(REFCAP)	Decoupling capacitor on REFCAPA, REFCAPB				10		µF
	Turn-on time	C_(REFCAP) = 10 µF, C_{(REFIN_REFOUT)} = 10 µF			25		ms
EXTERNAL REFERENCE INPUT (REFSEL = 0)
V_{REFIO_EXT}	External reference voltage on REFIO (configured as input)			2.475	2.5	2.525	V
	Reference input impedance				100		MΩ
	Reference input capacitance				10		pF
POWER-SUPPLY REQUIREMENTS
AVDD	Analog power-supply voltage	Analog supply		4.75	5	5.25	V
DVDD	Digital power-supply voltage	Digital supply range		2.3	3.3	AVDD	V
I_{AVDD_DYN}	Analog supply current (operational)	AVDD = 5 V, f_S = 500 kSPS, internal reference			22.8	30.8	mA
I_{AVDD_DYN}	Analog supply current (operational)	AVDD = 5 V, f_S = 500 kSPS, external reference			22.2	30	mA
I_{AVDD_STC}	Analog supply current (static)	AVDD = 5 V, internal reference, device not converting			12.7	17.4	mA
I_{AVDD_STC}	Analog supply current (static)	AVDD = 5 V, external reference, device not converting			12.3	16.7	mA
I_{AVDD_STDBY}	AVDD supply STANDBY current	At AVDD = 5 V, device in STDBY mode, internal reference			4.2	5.5	mA
I_{AVDD_STDBY}	AVDD supply STANDBY current	At AVDD = 5 V, device in STDBY mode, external reference			3.8	5	mA
I_{AVDD_PWR_ DN}	AVDD supply power-down current	At AVDD = 5 V, device in PWR_DN, internal or external reference, T_A = –40°C to +85°C			0.2	6	µA
I_{DVDD_DYN}	Digital supply current	DVDD = 3.3 V, f_S = 500 kSPS			0.2	0.33	mA
I_{DVDD_STDBY}	DVDD supply STANDBY current	At AVDD = 5 V, device in STDBY mode			0.05	1.5	µA
I_{DVDD_PWR-DN}	DVDD supply power-down current	At AVDD = 5 V, device in PWR_DN mode			0.05	1.5	µA
DIGITAL INPUTS (CMOS)
V_IH	Digital high input voltage logic level	DVDD > 2.3 V		0.8 × DVDD		DVDD + 0.3	V
V_IL	Digital low input voltage logic level	DVDD > 2.3 V		–0.3		0.2 × DVDD	V
	Input leakage current				100		nA
	Input pin capacitance				5		pF
DIGITAL OUTPUTS (CMOS)
V_OH	Digital high output voltage logic level	I_O = 100-µA source		0.8 × DVDD		DVDD	V
V_OL	Digital low output voltage logic level	I_O = 100-µA sink		0		0.2 × DVDD	V
	Floating state leakage current	Only for SDO			1		µA
	Internal pin capacitance				5		pF
TEMPERATURE RANGE
T_A	Operating free-air temperature			–40		125	°C

(1) Ideal input span, does not include gain or offset error.

(2) LSB = least significant bit.

(3) Device specifications are dependent on input ranges, irrespective of whether programming is done by pins or SPI registers.

(4) Calculated on the first nine harmonics of the input frequency.

(5) This parameter is the endpoint INL, not best-fit INL.

(6) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel.

(7) Does not include the variation in voltage resulting from solder shift effects.

(8) Recommended to use an X7R-grade, 0603-size ceramic capacitor for optimum performance (see the Layout Guidelines section).

(9) Gain error is calculated after adjusting for offset error, which implies that the positive full-scale error = negative full-scale error = gain error ÷ 2.