The ADS8588H supports data read operation when the BUSY output is high and the internal ADC is converting. The ADC outputs conversion results for previous samples if data read back is performed during an ongoing conversion. Any of the three interface modes (parallel, parallel byte, or serial) in any combination of oversampling modes can be used to read the device output during an ongoing conversion. The data read back during conversion mode allows faster throughput to be achieved from the device. There is no degradation in performance if data are read from the device during the conversion process using any of the three interface modes.

The Timing Requirements: Data Read Operation table describes the timing diagram for data read back during conversion. The timing specification t_{DZ_CSBSY} (the delay between the rising edge of the CS signal and the falling edge of the BUSY signal) must be met because the output data registers are updated with the current conversion results just before the falling edge of the BUSY signal and any read operation during this time can corrupt the register update.