The device features the multiSPI digital interface for communication and data transfer between the device and the host controller. The multiSPI interface supports many data transfer protocols that the host uses to exchange data and commands with the device. The host can transfer data into the device using one of the standard SPI modes. However, the device can be configured to output data in a number of ways to suit the application demands of throughput and latency. The data output in these modes can be controlled either by the host or the device, and the timing can either be system synchronous or source synchronous. For detailed explanation of the supported data transfer protocols, see the Section 7.5.4 section.

This section describes the main components of the digital interface module as well as supported configurations and protocols. As shown in Figure 7-19, the interface module is comprised of shift registers (both input and output), configuration registers, and a protocol unit. During any particular data frame, data are transferred both into and out of the device. As a result, the host always perceives the device as a 32-bit input-output shift register, as shown in Figure 7-19.

Figure 7-19 Device Interface Module

The Section 5 section provides descriptions of the interface pins; the Section 7.5.1 section details the functions of shift registers, the SCLK counter, and the command processor; the Data Transfer Protocols section details supported protocols; and the Section 7.6 section explains the configuration registers and bit settings.