米6体育平台手机版

ZHCSFU0B December 2016 – March 2021 ADS8661 , ADS8665

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机械数据 (封装 | 引脚)

PW|16
- MPDS361A

散热焊盘机械数据 (封装 | 引脚)

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6.5 Electrical Characteristics

all minimum and maximum specifications are at T_A = –40°C to +125°C; typical specifications are at T_A = 25°C; AVDD = 5 V, DVDD = 3.3 V, V_REF = 4.096 V (internal), and maximum throughput (unless otherwise noted)

PARAMETER			TEST CONDITIONS		MIN	TYP	MAX	UNIT
ANALOG INPUTS
V_IN	Full-scale input span⁽¹⁾ (AIN_P to AIN_GND)		Input range = ±3 × V_REF		–12.288		12.288	V
			Input range = ±2.5 × V_REF		–10.24		10.24
			Input range = ±1.5 × V_REF		–6.144		6.144
			Input range = ±1.25 × V_REF		–5.12		5.12
			Input range = ±0.625 × V_REF		–2.56		2.56
			Input range = 3 × V_REF		0		12.288
			Input range = 2.5 × V_REF		0		10.24
			Input range = 1.5 × V_REF		0		6.144
			Input range = 1.25 × V_REF		0		5.12
AIN_P	Operating input range		Input range = ±3 × V_REF		–12.288		12.288	V
			Input range = ±2.5 × V_REF		–10.24		10.24
			Input range = ±1.5 × V_REF		–6.144		6.144
			Input range = ±1.25 × V_REF		–5.12		5.12
			Input range = ±0.625 × V_REF		–2.56		2.56
			Input range = 3 × V_REF		0		12.288
			Input range = 2.5 × V_REF		0		10.24
			Input range = 1.5 × V_REF		0		6.144
			Input range = 1.25 × V_REF		0		5.12
AIN_GND	Operating input range		All input ranges		–0.1	0	0.1	V
R_IN	Input impedance		At T_A = 25°C	Input range = ±3 × V_REF	1.02	1.2	1.38	MΩ
				Input range = ±1.5 × V_REF	1.02	1.2	1.38
				Input range = 3 × V_REF	1.02	1.2	1.38
				Input range = 1.5 × V_REF	1.02	1.2	1.38
				Input range = ±2.5 × V_REF	0.85	1	1.15
				Input range = ±1.25 × V_REF	0.85	1	1.15
				Input range = ±0.625 × V_REF	0.85	1	1.15
				Input range = 2.5 × V_REF	0.85	1	1.15
				Input range = 1.25 × V_REF	0.85	1	1.15
	Input impedance drift					7	25	ppm/°C
I_IN	Input current		With voltage at the AIN_P pin = V_IN	Input range = ±3 × V_REF	(V_IN – 2.5) / R_IN			µA
				Input range = ±2.5 × V_REF	(V_IN – 2.2) / R_IN
				Input range = ±1.5 × V_REF	(V_IN – 2.0) / R_IN
				Input range = ±1.25 × V_REF	(V_IN – 2.0) / R_IN
				Input range = ±0.625 × V_REF	(V_IN – 1.6) / R_IN
				Input range = 3 × V_REF	(V_IN – 2.6) / R_IN
				Input range = 2.5 × V_REF	(V_IN – 2.5) / R_IN
				Input range = 1.5 × V_REF	(V_IN – 2.7) / R_IN
				Input range = 1.25 × V_REF	(V_IN – 2.5) / R_IN
INPUT OVERVOLTAGE PROTECTION CIRCUIT
V_OVP	All input ranges		AVDD = 5 V, all input ranges		–20		20	V
V_OVP	All input ranges		AVDD = floating, all input ranges		–15		15	V
INPUT BANDWIDTH
f_{–3 dB}	Small-signal Input bandwidth	–3 dB	All input ranges			15		kHz
f_{–0.1 dB}	Small-signal Input bandwidth	–0.1 dB	All input ranges			2.5		kHz
SYSTEM PERFORMANCE
	Resolution				12			Bits
NMC	No missing codes				12			Bits
DNL	Differential nonlinearity⁽⁴⁾		All input ranges		–0.35	±0.1	0.35	LSB
INL	Integral nonlinearity⁽⁴⁾		All input ranges		–0.35	±0.15	0.35	LSB
E_O	Offset error⁽²⁾		At T_A = 25°C	All bipolar ranges⁽⁸⁾	–1	±0.2	1	mV
E_O	Offset error⁽²⁾		At T_A = 25°C	All unipolar ranges⁽⁹⁾	–2	±0.2	2	mV
	Offset error drift with temperature		All input ranges		–3	±0.75	3	ppm/°C
E_G	Gain error⁽⁵⁾		At T_A = 25°C, all input ranges		–0.025	±0.01	0.025	%FSR
	Gain error drift with temperature⁽⁶⁾		All input ranges		–5	±1	5	ppm/°C
DYNAMIC CHARACTERISTICS
SNR	Signal-to-noise ratio⁽⁷⁾		All input ranges		73	73.5		dB
THD	Total harmonic distortion⁽³⁾⁽⁷⁾		All input ranges			–102		dB
SINAD	Signal-to-noise + distortion⁽⁷⁾		All input ranges		72.9	73.4		dB
SFDR	Spurious-free dynamic range⁽⁷⁾		All input ranges			103		dB
SAMPLING DYNAMICS
t_CONV	Conversion time		ADS8661				550	ns
t_CONV	Conversion time		ADS8665				1000	ns
t_ACQ	Acquisition time		ADS8661		250			ns
t_ACQ	Acquisition time		ADS8665		1000			ns
f_cycle	Maximum throughput rate without latency		ADS8661				1250	kSPS
f_cycle	Maximum throughput rate without latency		ADS8665				500	kSPS
INTERNAL REFERENCE OUTPUT
V_REFIO	On the REFIO pin (configured as an output)		At T_A = 25°C		4.095	4.096	4.097	V
dV_REFIO/dT_A	Internal reference temperature drift					4		ppm/°C
C_{OUT_REFIO}	Decoupling capacitor on REFIO pin				4.7			µF
V_REFCAP	Reference voltage to the ADC (on the REFCAP pin)		At T_A = 25°C		4.095	4.096	4.097	V
	REFCAP temperature drift					0.5	2	ppm/°C
C_{OUT_REFCAP}	Decoupling capacitor on REFCAP pin				10			μF
	Turn-on time		C_{OUT_REFCAP} = 10 µF, C_{OUT_REFIO} = 10 µF			20		ms
EXTERNAL REFERENCE INPUT
V_{REFIO_EXT}	External reference voltage on REFIO		REFIO pin configured as an input		4.046	4.096	4.146	V
AVDD COMPARATOR
V_{TH_HIGH}	High threshold voltage					5.3		V
V_{TH_LOW}	Low threshold voltage					4.7		V
POWER-SUPPLY REQUIREMENTS
AVDD	Analog power-supply voltage				4.75	5	5.25	V
DVDD	Digital power-supply voltage		Operating range		1.65	3.3	AVDD
DVDD	Digital power-supply voltage		Supply range for specified performance		2.7	3.3	AVDD
I_{AVDD_DYN}	Analog supply current, device converting at maximum throughput		Internal reference	ADS8661		7	9	mA
			Internal reference	ADS8665		4.9	6.5
			External reference	ADS8661		5.8	7.25
			External reference	ADS8665		3.7	4.5
I_{AVDD_STC}	Analog supply current, device not converting		Internal reference			2.9	4	mA
I_{AVDD_STC}	Analog supply current, device not converting		External reference			1.7	2.25	mA
I_{AVDD_STDBY}	Analog supply current, device in STANDBY mode		Internal reference			2.8		mA
I_{AVDD_STDBY}	Analog supply current, device in STANDBY mode		External reference			1.6		mA
I_{AVDD_PD}	Analog supply current, device in PD mode		Internal reference			10		μA
I_{AVDD_PD}	Analog supply current, device in PD mode		External reference			10		μA
I_{DVDD_DYN}	Digital supply current, maximum throughput					0.2	0.25	mA
I_{DVDD_STDBY}	Digital supply current, device in STANDBY mode					1		μA
I_{DVDD_PD}	Digital supply current, device in PD mode					1		μA
DIGITAL INPUTS (CMOS)
V_IH	Digital high input voltage logic level		DVDD > 2.35 V		0.7 × DVDD		DVDD + 0.3	V
V_IH	Digital high input voltage logic level		DVDD ≤ 2.35 V		0.8 × DVDD		DVDD + 0.3	V
V_IL	Digital low input voltage logic level		DVDD > 2.35 V		–0.3		0.3 × DVDD	V
V_IL	Digital low input voltage logic level		DVDD ≤ 2.35 V		–0.3		0.2 × DVDD	V
	Input leakage current					100		nA
	Input pin capacitance					5		pF
DIGITAL OUTPUTS (CMOS)
V_OH	Digital high output voltage logic level		I_O = 500-μA source		0.8 × DVDD		DVDD	V
V_OL	Digital low output voltage logic level		I_O = 500-μA sink		0		0.2 × DVDD	V
	Floating state leakage current		Only for digital output pins			1		µA
	Internal pin capacitance					5		pF
TEMPERATURE RANGE
T_A	Operating free-air temperature				–40		125	°C

(1) Ideal input span, does not include gain or offset error.

(2) Measured relative to actual measured reference.

(3) Calculated on the first nine harmonics of the input frequency.

(4) This specification indicates the endpoint INL, not best-fit INL.

(5) Excludes internal reference accuracy error.

(6) Excludes internal reference temperature drift.

(7) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with a 1-kHz input signal 0.25 dB below full-scale, unless otherwise specified.

(8) Bipolar ranges are ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V.

(9) Unipolar ranges are 0 V–12.288 V, 0 V–10.24 V, 0 V–6.144 V, and 0 V–5.12 V.