ZHCSDW0 July   2015 ADS8664 , ADS8668

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
      2. 8.3.2  Analog Input Impedance
      3. 8.3.3  Input Overvoltage Protection Circuit
      4. 8.3.4  Programmable Gain Amplifier (PGA)
      5. 8.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 8.3.6  ADC Driver
      7. 8.3.7  Multiplexer (MUX)
      8. 8.3.8  Reference
        1. 8.3.8.1 Internal Reference
        2. 8.3.8.2 External Reference
      9. 8.3.9  Auxiliary Channel
        1. 8.3.9.1 Input Driver for the AUX Channel
      10. 8.3.10 ADC Transfer Function
      11. 8.3.11 Alarm Feature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Interface
        1. 8.4.1.1 Digital Pin Description
          1. 8.4.1.1.1 CS (Input)
          2. 8.4.1.1.2 SCLK (Input)
          3. 8.4.1.1.3 SDI (Input)
          4. 8.4.1.1.4 SDO (Output)
          5. 8.4.1.1.5 DAISY (Input)
          6. 8.4.1.1.6 RST/PD (Input)
        2. 8.4.1.2 Data Acquisition Example
        3. 8.4.1.3 Host-to-Device Connection Topologies
          1. 8.4.1.3.1 Daisy-Chain Topology
          2. 8.4.1.3.2 Star Topology
      2. 8.4.2 Device Modes
        1. 8.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 8.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 8.4.2.3 STANDBY Mode (STDBY)
        4. 8.4.2.4 Power-Down Mode (PWR_DN)
        5. 8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)
        6. 8.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 8.4.2.7 Channel Sequencing Modes
        8. 8.4.2.8 Reset Program Registers (RST)
    5. 8.5 Register Maps
      1. 8.5.1 Command Register Description
      2. 8.5.2 Program Register Description
        1. 8.5.2.1 Program Register Read/Write Operation
        2. 8.5.2.2 Program Register Map
        3. 8.5.2.3 Program Register Descriptions
          1. 8.5.2.3.1 Auto-Scan Sequencing Control Registers
            1. 8.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)
            2. 8.5.2.3.1.2 Channel Power Down Register (address = 02h)
          2. 8.5.2.3.2 Device Features Selection Control Register (address = 03h)
          3. 8.5.2.3.3 Range Select Registers (addresses 05h-0Ch)
          4. 8.5.2.3.4 Alarm Flag Registers (Read-Only)
            1. 8.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)
            2. 8.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          5. 8.5.2.3.5 Alarm Threshold Setting Registers
          6. 8.5.2.3.6 Command Read-Back Register (address = 3Fh)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 12-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DBT Package
38-Pin TSSOP
Top View (Not to Scale)
ADS8664 ADS8668 po_ads8664_ads8668_sbas492.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
ADS8664 ADS8668
1 SDI Digital input Data input for serial communication.
2 RST/PD Digital input Active low logic input.
Dual functionality to reset or power-down the device.
3 DAISY Digital input Chain the data input during serial communication in daisy-chain mode.
4 REFSEL Digital input Active low logic input to enable the internal reference.
When low, the internal reference is enabled;
REFIO becomes an output that includes the VREF voltage.
When high, the internal reference is disabled;
REFIO becomes an input to apply the external VREF voltage.
5 REFIO Analog input, output Internal reference output and external reference input pin. Decouple with REFGND on pin 6.
6 REFGND Power supply Reference GND pin; short to the analog GND plane.
Decouple with REFIO on pin 5 and REFCAP on pin 7.
7 REFCAP Analog output ADC reference decoupling capacitor pin. Decouple with REFGND on pin 6.
8 AGND Power supply Analog ground pin. Decouple with AVDD on pin 9.
9 AVDD Power supply Analog supply pin. Decouple with AGND on pin 8.
10 AUX_IN Analog input Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11.
11 AUX_GND Analog input Auxiliary input channel: negative input. Decouple with AUX_IN on pin 10.
12 NC AIN_6P Analog input Analog input channel 6, positive input. Decouple with AIN_6GND on pin 13.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
13 NC AIN_6GND Analog input Analog input channel 6, negative input. Decouple with AIN_6P on pin 12.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
14 NC AIN_7P Analog input Analog input channel 7, positive input. Decouple with AIN_7GND on pin 15.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
15 NC AIN_7GND Analog input Analog input channel 7, negative input. Decouple with AIN_7P on pin 14.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
16 AIN_0P Analog input Analog input channel 0, positive input. Decouple with AIN_0GND on pin 17.
17 AIN_0GND Analog input Analog input channel 0, negative input. Decouple with AIN_0P on pin 16.
18 AIN_1P Analog input Analog input channel 1, positive input. Decouple with AIN_1GND on pin 19.
19 AIN_1GND Analog input Analog input channel 1, negative input. Decouple with AIN_1P on pin 18.
20 AIN2_GND Analog input Analog input channel 2, negative input. Decouple with AIN_2P on pin 21.
21 AIN_2P Analog input Analog input channel 2, positive input. Decouple with AIN_2GND on pin 20.
22 AIN_3GND Analog input Analog input channel 3, negative input. Decouple with AIN_3P on pin 23.
23 AIN_3P Analog input Analog input channel 3, positive input. Decouple with AIN_3GND on pin 22.
24 NC AIN_4GND Analog input Analog input channel 4, negative input. Decouple with AIN_4P on pin 25.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
25 NC AIN_4P Analog input Analog input channel 4, positive input. Decouple with AIN_4GND on pin 24.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
26 NC AIN_5GND Analog input Analog input channel 5, negative input. Decouple with AIN_5P on pin 27.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
27 NC AIN_5P Analog input Analog input channel 5, positive input. Decouple with AIN_5GND on pin 26.
No connection for the ADS8664; this pin can be left floating or connected to AGND.
28 AGND Power supply Analog ground pin
29 AGND Power supply Analog ground pin
30 AVDD Power supply Analog supply pin. Decouple with AGND on pin 31.
31 AGND Power supply Analog ground pin. Decouple with AVDD on pin 30.
32 AGND Power supply Analog ground pin
33 DGND Power supply Digital ground pin. Decouple with DVDD on pin 34.
34 DVDD Power supply Digital supply pin. Decouple with DGND on pin 33.
35 ALARM Digital output Active high alarm output
36 SDO Digital output Data output for serial communication
37 SCLK Digital input Clock input for serial communication
38 CS Digital input Active low logic input; chip-select signal
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