ZHCSEV3E February 2016 – August 2022 ADS8681 , ADS8685 , ADS8689
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements: Conversion Cycle
- 6.7 Timing Requirements: Asynchronous Reset
- 6.8 Timing Requirements: SPI-Compatible Serial Interface
- 6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock)
- 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
- 6.11 Timing Diagrams
- 6.12 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Device Configuration and Register Maps
- 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
- 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
- 7.6.1.3 SDI_CTL_REG Register (address = 08h)
- 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
- 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
- 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
- 7.6.1.7 ALARM_REG Register (address = 20h)
- 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
- 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
- 7.6.1
Device Configuration and Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
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- RUM|16
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7.3.1 Analog Input Structure
The device features a pseudo-differential input structure, meaning that the single-ended analog input signal is applied at the positive input AIN_P and the negative input AIN_GND is tied to GND. Figure 7-1 shows the simplified circuit schematic for the AFE circuit, including the input overvoltage protection circuit, PGA, low-pass filter (LPF), and high-speed ADC driver.
Figure 7-1 Simplified Analog Front-End Circuit SchematicThe device can support multiple unipolar or bipolar, single-ended input voltage ranges based on the configuration of the program registers. As explained in the RANGE_SEL_REG register, the input voltage range can be configured to bipolar ±3 × VREF, ±2.5 × VREF, ±1.5 × VREF, ±1.25 × VREF, and ±0.625 × VREF or unipolar 0 to 3 × VREF, 0 to 2.5 × VREF, 0 to 1.5 × VREF and 0 to 1.25 × VREF. With the internal or external reference voltage set to 4.096 V, the input ranges of the device can be configured to bipolar ranges of ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V or unipolar ranges of 0 V to 12.288 V, 0 V to 10.24 V, 0 V to 6.144 V, and 0 V to 5.12 V.
The device samples the voltage difference (AIN_P – AIN_GND) between the analog input and the AIN_GND pin. The device allows a ±0.1-V range on the AIN_GND pin. This feature is useful in modular systems where the sensor or signal-conditioning block is further away from the ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC ground is possible. In such cases, running separate wires from the AIN_GND pin of the device to the sensor or signal-conditioning ground is recommended. In order to obtain optimum performance, the input currents and impedances along each input path are recommended to be matched. The two single-ended signals to AIN_P and AIN_GND must be routed as symmetrically as possible from the signal source to the ADC input pins.
If the analog input pin (AIN_P) to the device is left floating, the output of the ADC corresponds to an internal biasing voltage. The output from the ADC must be considered as invalid if the device is operated with floating input pins. This condition does not cause any damage to the device, which becomes fully functional when a valid input voltage is applied to the pins.