Table 1. Input Overvoltage Protection Limits When AVDD = 5 V or Offers a Low Impedance of < 30 kΩ⁽¹⁾

Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 kΩ⁽¹⁾

Table 3. Input Range Selection Bits Configuration

8.3.8.1 Internal Reference

The devices have an internal 4.096-V (nominal value) reference. In order to select the internal reference, the REFSEL pin must be tied low or connected to AGND. When the internal reference is used, REFIO (pin 5) becomes an output pin with the internal reference value. Placing a 10-µF (minimum) decoupling capacitor between the REFIO pin and REFGND (pin 6) is recommended, as shown in Figure 73. The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value allows higher reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIO pin to drive external ac or dc loads because REFIO has limited current output capability. The REFIO pin can be used as a source if followed by a suitable op amp buffer (such as the OPA320).

Figure 73. Device Connections for Using an Internal 4.096-V Reference

The device internal reference is trimmed to a maximum initial accuracy of ±1 mV. The histogram in Figure 74 shows the distribution of the internal voltage reference output taken from more than 3300 production devices.

Figure 74. Internal Reference Accuracy at Room Temperature Histogram

The initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical or thermal stress. Heating the device when being soldered to a PCB and any subsequent solder reflow is a primary cause for shifts in the V_REF value. The main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach material, and molding compound, as well as the layout of the device itself.

In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the manufacturer's suggested reflow profile, as explained in application report SNOA550. The internal voltage reference output is measured before and after the reflow process and the typical shift in value is shown in Figure 75. Although all tested units exhibit a positive shift in their output voltages, negative shifts are also possible. Note that the histogram in Figure 75 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8684A and ADS8688A in the second pass to minimize device exposure to thermal stress.

Figure 75. Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –40°C to 125°C. Figure 76 shows the variation of the internal reference voltage across temperature for different values of the AVDD supply voltage. The typical specified value of the reference voltage drift over temperature is 6 ppm/°C (Figure 77) and the maximum specified temperature drift is equal to 10 ppm/°C.

Figure 76. Variation of the Internal Reference Output (REFIO) Across Supply and Temperature

AVDD = 5 V, number of devices = 30, ΔT = –40°C to 125°C

Figure 77. Internal Reference Temperature Drift Histogram

8.3.8.2 External Reference

For applications that require a better reference voltage or a common reference voltage for multiple devices, the ADS8684A and ADS8688A offer a provision to use an external reference along with an internal buffer to drive the ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin high or connect this pin to the DVDD supply. In this mode, an external 4.096-V reference must be applied at REFIO (pin 5), which becomes an input pin. Any low-power, low-drift, or small-size external reference can be used in this mode because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin, which is internally connected to the ADC reference input. The output of the external reference must be appropriately filtered to minimize the resulting effect of the reference noise on system performance. A typical connection diagram for this mode is shown in Figure 78.

Figure 78. Device Connections for Using an External 4.096-V Reference

The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must be placed between REFCAP (pin 7) and REFGND (pin 6). Place another capacitor of 1 µF as close to the REFCAP pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac or dc loads because of the limited current output capability of this buffer.

The performance of the internal buffer output is very stable across the entire operating temperature range of –40°C to 125°C. Figure 79 shows the variation in the REFCAP output across temperature for different values of the AVDD supply voltage. The typical specified value of the reference buffer drift over temperature is 1 ppm/°C (Figure 80) and the maximum specified temperature drift is equal to 1.5 ppm/°C.

Figure 79. Variation of the Reference Buffer Output (REFCAP) vs Supply and Temperature

AVDD = 5 V, number of devices = 30, ΔT = –40°C to 125°C

Figure 80. Reference Buffer Temperature Drift Histogram

8.3.9.1 Input Driver for the AUX Channel

For applications that use the AUX input channels at high throughput and high input frequency, a driving amplifier with low output impedance is required to meet the ac performance of the internal 16-bit ADC. Some key specifications of the input driving amplifier are discussed below:

• Small-signal bandwidth. The small-signal bandwidth of the input driving amplifier must be much higher than the bandwidth of the AUX input to ensure that there is no attenuation of the input signal resulting from the bandwidth limitation of the amplifier. In a typical data acquisition system, a low cut-off frequency, antialiasing filter is used at the inputs of a high-resolution ADC. The amplifier driving the antialiasing filter must have a low closed-loop output impedance for stability, thus implying a higher gain bandwidth for the amplifier. Higher small-signal bandwidth also minimizes the harmonic distortion at higher input frequencies. In general, the amplifier bandwidth requirements can be calculated on the basis of Equation 1.
Equation 1.
where
• f_–3dB is the 3-dB bandwidth of the RC filter.
• Distortion. In order to achieve the distortion performance of the AUX channel, the distortion of the input driver must be at least 10 dB lower than the specified distortion of the internal ADC, as shown in Equation 2.
Equation 2.
• Noise. Careful considerations must be made to select a low-noise, front-end amplifier in order to prevent any degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the front-end circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-limited by the low cut-off frequency of the input antialiasing filter, as explained in Equation 3.
Equation 3.
where
• V_{1 / f_AMP_PP} is the peak-to-peak flicker noise,
• e_{n_RMS} is the amplifier broadband noise density in nV/√Hz, and
• N_G is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.

Table 4. ADC LSB Values for Different Input Ranges (V_REF = 4.096 V)

8.4.1.1 Digital Pin Description

The digital data interface for the ADS8684A and ADS8688A is shown in Figure 89.

Figure 89. Pin Configuration for the Digital Interface

The signals shown in Figure 89 are summarized as follows:

8.4.1.1.6 RST/PD (Input)

RST/PD is a dual-function pin. Figure 90 shows the timing of this pin and Table 5 explains the usage of this pin.

Figure 90. RST/PD Pin Timing

Table 5. RST/PD Pin Functionality

CONDITION	DEVICE MODE
40 ns < tPL_RST_PD ≤ 100 ns	The device is in RST mode and does not enter PWR_DN mode.
100 ns < tPL_RST_PD < 400 ns	The device is in RST mode and may or may not enter PWR_DN mode. NOTE: This setting is not recommended.
tPL_RST_PD ≥ 400 ns	The device enters PWR_DN mode and the program registers are reset to default value.

The devices can be placed into power-down (PWR_DN) mode by pulling the RST/PD pin to a logic low state for at least 400 ns. The RST/PD pin is asynchronous to the clock; thus, RST/PD can be triggered at any time regardless of the status of other pins (including the analog input channels). When the device is in power-down mode, any activity on the digital input pins (apart from the RST/PD pin) is ignored.

The program registers in the device can be reset to their default values (RST) by pulling the RST/PD pin to a logic low state for no longer than 100 ns. This input is asynchronous to the clock. When RST/PD is pulled back to a logic high state, the devices are placed in normal mode. One valid write operation must be executed on the program register in order to configure the device, followed by an appropriate command (AUTO_RST or MAN) to initiate conversions.

When the RST/PD pin is pulled back to a logic high level, the devices wake-up in a default state in which the program registers are reset to their default values.

8.4.1.2 Data Acquisition Example

This section provides an example of how a host processor can use the device interface to configure the device internal registers as well as convert and acquire data for sampling a particular input channel. The timing diagram shown in Figure 91 provides further details.

Figure 91. Device Operation Using the Serial Interface Timing Diagram

There are four events shown in Figure 91. These events are described below:

• Event 1: The host initiates a data conversion frame through a falling edge of the CS signal. The analog input signal at the instant of the CS falling edge is sampled by the ADC and conversion is performed using an internal oscillator clock. The analog input channel converted during this frame is selected in the previous data frame. The internal register settings of the device for the next conversion can be input during this data frame using the SDI and SCLK inputs. Initiate SCLK at this instant and latch data on the SDI line into the device on every SCLK falling edge for the next 16 SCLK cycles. At this instant, SDO goes low because the device does not output internal conversion data on the SDO line during the first 16 SCLK cycles.
• Event 2: During the first 16 SCLK cycles, the device completes the internal conversion process and data are now ready within the converter. However, the device does not output data bits on SDO until the 16th falling edge appears on the SCLK input. Because the ADC conversion time is fixed (the maximum value is given in the Electrical Characteristics table), the 16th SCLK falling edge must appear after the internal conversion is over, otherwise data output from the device is incorrect. Therefore, the SCLK frequency cannot exceed a maximum value, as provided in the Timing Requirements: Serial Interface table.
• Event 3: At the 16th falling edge of the SCLK signal, the device reads the LSB of the input word on the SDI line. The device does not read anything from the SDI line for the remaining data frame. On the same edge, the MSB of the conversion data is output on the SDO line and can be read by the host processor on the subsequent falling edge of the SCLK signal. For 16 bits of output data, the LSB can be read on the 32nd SCLK falling edge. The SDO outputs 0 on subsequent SCLK falling edges until the next conversion is initiated.
• Event 4: When the internal data from the device is received, the host terminates the data frame by deactivating the CS signal to high. The SDO output goes into a Hi-Z state until the next data frame is initiated, as explained in Event 1.

8.4.1.3 Host-to-Device Connection Topologies

The digital interface of the ADS8684A and ADS8688A offers a lot of flexibility in the ways that a host controller can exchange data or commands with the device. A typical connection between a host controller and a stand-alone device is illustrated in Figure 89. However, there are applications that require multiple ADCs but the host controller has limited interfacing capability. This section describes two connection topologies that can be used to address the requirements of such applications.

8.4.1.3.1 Daisy-Chain Topology

A typical connection diagram showing multiple devices in daisy-chain mode is shown in Figure 92. The CS, SCLK, and SDI inputs of all devices are connected together and controlled by a single CS, SCLK, and SDO pin of the host controller, respectively. The DAISY₁ input pin of the first ADC in the chain is connected to DGND, the SDO₁ output pin is connected to the DAISY₂ input of ADC₂, and so forth. The SDO_N pin of the Nth ADC in the chain is connected to the SDI pin of the host controller. The devices do not require any special hardware or software configuration to enter daisy-chain mode.

Figure 92. Daisy-Chain Connection Schematic

A typical timing diagram for three devices connected in daisy-chain mode is shown in Figure 93.

Figure 93. Three Devices Connected in Daisy-Chain Mode Timing Diagram

At the falling edge of the CS signal, all devices sample the input signal at their respective selected channels and enter into conversion phase. For the first 16 SCLK cycles, the internal register settings for the next conversion can be entered using the SDI line that is common to all devices in the chain. During this time period, the SDO outputs for all devices remain low. At the end of conversion, every ADC in the chain loads its own conversion result into an internal 16-bit shift register. At the 16th SCLK falling edge, every ADC in the chain outputs the MSB bit on its own SDO output pin. On every subsequent SCLK falling edge, the internal shift register of each ADC latches the data available on its DAISY pin and shifts out the next bit of data on its SDO pin. Therefore, the digital host receives the data of ADC_N, followed by the data of ADC_N–1, and so forth (in MSB-first fashion). In total, a minimum of 16 × N SCLK falling edges are required to capture the outputs of all N devices in the chain. This example uses three devices in a daisy-chain connection, so 3 × 16 = 48 SCLK cycles are required to capture the outputs of all devices in the chain along with the 16 SCLK cycles to input the register settings for the next conversion, resulting in a total of 64 SCLK cycles for the entire data frame. Note that the overall throughput of the system is proportionally reduced with the number of devices connected in a daisy-chain configuration.

The following points must be noted about the daisy-chain configuration illustrated in Figure 92:

• The SDI pins for all devices are connected together so each device operates with the same internal configuration. This limitation can be overcome by spending additional host controller resources to control theCS or SDI input of devices with unique configurations.
• If the number of devices connected in daisy-chain is more than four, loading increases on the shared output lines from the host controller (CS, SDO, and SCLK). This increased loading can lead to digital timing errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller before feeding the shared digital lines into additional devices.

8.4.1.3.2 Star Topology

A typical connection diagram showing multiple devices in the star topology is shown in Figure 94. The SDI and SCLK inputs of all devices are connected together and are controlled by a single SDO and SCLK pin of the host controller, respectively. Similarly, the SDO outputs of all devices are tied together and connected to the SDI input pin of the host controller. The CS input pin of each device is individually controlled by separate CS control lines from the host controller.

Figure 94. Star Topology Connection Schematic

The timing diagram for a typical data frame in the star topology is the same as in a stand-alone device operation, as illustrated in Figure 91. The data frame for a particular device starts with the falling edge of the CS signal and ends when the CS signal goes high. Because the host controller provides separate CS control signals for each device in this topology, the user can select the devices in any order and initiate a conversion by bringing down the CS signal for that particular device. As explained in Figure 91, when CS goes high at the end of each data frame, the SDO output of the device is placed into a Hi-Z state. Therefore, the shared SDO line in the star topology is controlled only by the device with an active data frame (CS is low). In order to avoid any conflict related to multiple devices driving the SDO line at the same time, ensure that the host controller pulls down the CS signal for only one device at any particular time.

TI recommends connecting a maximum of four devices in the star topology. Beyond that, loading may increase on the shared output lines from the host controller (SDO and SCLK). This loading can lead to digital timing errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller before being fed into additional devices.

8.4.2.1 Continued Operation in the Selected Mode (NO_OP)

Holding the SDI line low continuously (equivalent to writing a 0 to all 16 bits) during device operation continues device operation in the last selected mode (STDBY, PWR_DN, AUTO_RST, or MAN_Ch_n). In this mode, the device follows the same settings that are already configured in the program registers.

If a NO_OP condition occurs when the device is performing any read or write operation in the program register (PROG mode), then the device retains the current settings of the program registers. The device goes back to IDLE mode and waits for the user to enter a proper command to execute the program register read or write configuration.

8.4.2.2 Frame Abort Condition (FRAME_ABORT)

As explained in the Data Acquisition Example section, the device digital interface is designed such that each data frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit command word on the SDI line. The device waits to execute the command until the last bit of the command is received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If the CS signal goes high for any reason before the data transmission is complete, the device goes into an INVALID state and waits for a proper command to be written. This condition is called the FRAME_ABORT condition. When the device is operating in this INVALID mode, any read operation on the device returns invalid data on the SDO line. The output of the ALARM pin will continue to reflect the status of input signal on the previously selected channel.

8.4.2.3 STANDBY Mode (STDBY)

The devices support a low-power standby mode (STDBY) in which only part of the circuit is powered down. The internal reference and buffer is not powered down, and therefore, the devices can be quickly powered up in 20 µs on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not reset to the default values.

To enter STDBY mode, execute a valid write operation to the command register with a STDBY command of 8200h, as shown in Figure 96. The command is executed and the device enters STDBY mode on the next CS rising edge following this write operation. The device remains in STDBY mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected Mode section) during the subsequent data frames. When the device operates in STDBY mode, the program register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in STDBY mode. The program register read operation can take place normally during this mode.

Figure 96. Enter and Remain in STDBY Mode Timing Diagram

In order to exit STDBY mode a valid 16-bit write command must be executed to enter auto (AUTO_RST) or manual (MAN_CH_n) scan mode, as shown in Figure 97. The device starts exiting STDBY mode on the next CS rising edge. At the next CS falling edge, the device samples the analog input at the channel selected by the MAN_CH_n command or the first channel of the AUTO_RST mode sequence. To ensure that the input signal is sampled correctly, keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device internal circuitry can be fully powered up and biased properly before taking the sample. The data output for the selected channel can be read during the same data frame, as explained in Figure 91.

Figure 97. Exit STDBY Mode Timing Diagram

8.4.2.4 Power-Down Mode (PWR_DN)

The devices support a hardware and software power-down mode (PWR_DN) in which all internal circuitry is powered down, including the internal reference and buffer. A minimum time of 15 ms is required for the device to power up and convert the selected analog input channel after exiting PWR_DN mode, if the device is operating in the internal reference mode (REFSEL = 0). The hardware power mode for the device is explained in the RST/PD (Input) section. The primary difference between the hardware and software power-down modes is that the program registers are reset to default values when the devices wake up from hardware power-down, but the previous settings of the program registers are retained when the devices wake up from software power-down.

To enter PWR_DN mode using software, execute a valid write operation on the command register with a software PWR_DN command of 8300h, as shown in Figure 98. The command is executed and the device enters PWR_DN mode on the next CS rising edge following this write operation. The device remains in PWR_DN mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected Mode section) during the subsequent data frames. When the device operates in PWR_DN mode, the program register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in PWR_DN mode. The program register read operation can take place normally during this mode.

Figure 98. Enter and Remain in PWR_DN Mode Timing Diagram

In order to exit from PWR_DN mode a valid 16-bit write command must be executed, as shown in Figure 99. The device comes out of PWR_DN mode on the next CS rising edge. For operation in internal reference mode (REFSEL = 0), 15 ms are required for the device to power-up the reference and other internal circuits and settle to the required accuracy before valid conversion data are output for the selected input channel.

Figure 99. Exit PWR_DN Mode Timing Diagram

8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)

The devices can be programmed to scan the input signal on all analog channels automatically by writing a valid auto channel sequence with a reset (AUTO_RST, A000h) command in the command register, as explained in Figure 100. As shown in Figure 100, the CS signal can be pulled high immediately after the AUTO_RST command or after reading the output data of the frame. However, in order to accurately acquire and convert the input signal on the first selected channel in the next data frame, the command frame must be a complete frame of 32 SCLK cycles.

The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing control register (01h to 02h) in the program register; see the Program Register Map section. In this mode, the devices continuously cycle through the selected channels in ascending order, beginning with the lowest channel and converting all channels selected in the program register. On completion of the sequence, the devices return to the lowest count channel in the program register and repeat the sequence. The input voltage range for each channel in the auto-scan sequence can be configured by setting the Range Select Registers of the program registers.

Figure 100. Enter AUTO_RST Mode Timing Diagram

The devices remain in AUTO_RST mode if no other valid command is executed and SDI is kept low (see the Continued Operation in the Selected Mode (NO_OP) section) during subsequent data frames. If the AUTO_RST command is executed again at any time during this mode of operation, then the sequence of the scanned channels is reset. The devices return to the lowest count channel of the auto-scan sequence in the program register and repeat the sequence. The timing diagram in Figure 101 shows this behavior using an example in which channels 0 to 2 are selected in the auto sequence. For switching between AUTO_RST mode and MAN_Ch_n mode; see the Channel Sequencing Modes section.

Figure 101. Device Operation Example in AUTO_RST Mode

8.4.2.6 Manual Channel n Select (MAN_Ch_n)

The devices can be programmed to convert a particular analog input channel by operating in manual channel n scan mode (MAN_Ch_n). This programming is done by writing a valid manual channel n select command (MAN_Ch_n) in the command register, as shown in Figure 102. As shown in Figure 102, the CS signal can be pulled high immediately after the MAN_Ch_n command or after reading the output data of the frame. However, in order to accurately acquire and convert the input signal on the next channel, the command frame must be a complete frame of 32 SCLK cycles. See Table 6 for a list of commands to select individual channels during MAN_Ch_n mode.

Figure 102. Enter MAN_Ch_n Scan Mode Timing Diagram

The manual channel n select command (MAN_Ch_n) is executed and the devices sample the analog input on the selected channel on the CS falling edge of the next data frame following this write operation. The input voltage range for each channel in the MAN_Ch_n mode can be configured by setting the Range Select Registers in the program registers. The device continues to sample the analog input on the same channel if no other valid command is executed and SDI is kept low (see the Continued Operation in the Selected Mode (NO_OP) section) during subsequent data frames. The timing diagram in Figure 103 shows this behavior using an example in which channel 1 is selected in the manual sequencing mode. For switching between MAN_Ch_n mode and AUTO_RST mode; see the Channel Sequencing Modes section.

Figure 103. Device Operation in MAN_Ch_n Mode

8.4.2.7 Channel Sequencing Modes

The devices offer two channel sequencing modes: AUTO_RST and MAN_Ch_n.

In AUTO_RST mode, the channel number automatically increments in every subsequent frame. As explained in the Auto-Scan Sequencing Control Registers section, the analog inputs can be selected for an automatic scan with a register setting. The device automatically scans only the selected analog inputs in ascending order. The unselected analog input channels can also be powered down for optimizing power consumption in this mode of operation. The auto-mode sequence can be reset at any time during an automatic scan (using the AUTO_RST command). When the reset command is received, the ongoing auto-mode sequence is reset and restarts from the lowest selected channel in the sequence.

In MAN_Ch_n mode, the same input channel is selected during every data conversion frame. The input command words to select individual analog channels in MAN_Ch_n mode are listed in Table 6. If a particular input channel is selected during a data frame, then the analog inputs on the same channel are sampled during the next data frame. Figure 104 shows the SDI command sequence for transitions from AUTO_RST to MAN_Ch_n mode.

Figure 104. Transitioning from AUTO_RST to MAN_Ch_n Mode
(Channels 0 and 5 are Selected for Auto Sequence)

Figure 105 shows the SDI command sequence for transitions from MAN_Ch_n to AUTO_RST mode. Note that each SDI command is executed on the next CS falling edge. A RST command can be issued at any instant during any channel sequencing mode, after which the device is placed into a default power-up state in the next data frame.

Figure 105. Transitioning from MAN_Ch_n to AUTO_RST Mode
(Channels 0 and 5 are Selected for Auto Sequence)

8.4.2.8 Reset Program Registers (RST)

The devices support a hardware and software reset (RST) mode in which all program registers are reset to their default values. The devices can be put into RST mode using a hardware pin, as explained in the RST/PD (Input) section.

The device program registers can be reset to their default values during any data frame by executing a valid write operation on the command register with a RST command of 8500h, as shown in Figure 106. The device remains in RST mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected Mode (NO_OP) section) during the subsequent data frames. When the device operates in RST mode, the program register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in RST mode. The values of the program register can be read normally during this mode. A valid AUTO_RST or MAN_CH_n channel selection command must be executed for initiating a conversion on a particular analog channel using the default program register settings.

Figure 106. Reset Program Registers (RST) Timing Diagram

Table 6. Command Register Map

8.5.2.1 Program Register Read/Write Operation

The program register is a 16-bit read or write register. There must be a minimum of 24 SCLKs after the CS falling edge for any read or write operation to the program registers. When CS goes low, the SDO line goes low as well. The device receives the command (see Table 7 and Table 8) through SDI where the first seven bits (bits 15-9) represent the register address and the eighth bit (bit 8) is the write or read instruction.

For a write cycle, the next eight bits (bits 7-0) on SDI are the desired data for the addressed register. Over the next eight SCLK cycles, the device outputs this 8-bit data that is written into the register. This data readback allows verification to determine if the correct data are entered into the device. A typical timing diagram for a program register write cycle is shown in Figure 107.

Figure 107. Program Register Write Cycle Timing Diagram

For a read cycle, the next eight bits (bits 7-0) on SDI are don’t care bits and SDO stays low. From the 16th SCLK falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in MSB-first fashion. A typical timing diagram for a program register read cycle is shown in Figure 108.

Figure 108. Program Register Read Cycle Timing Diagram

8.5.2.2 Program Register Map

This section provides a bit-by-bit description of each program register.

8.5.2.3 Program Register Descriptions