ZHCSCR1B July   2014  – August 2014 ADS8684 , ADS8688

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
      2. 8.3.2  Analog Input Impedance
      3. 8.3.3  Input Overvoltage Protection Circuit
      4. 8.3.4  Programmable Gain Amplifier (PGA)
      5. 8.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 8.3.6  ADC Driver
      7. 8.3.7  Multiplexer (MUX)
      8. 8.3.8  Reference
        1. 8.3.8.1 Internal Reference
        2. 8.3.8.2 External Reference
      9. 8.3.9  Auxiliary Channel
        1. 8.3.9.1 Input Driver for the AUX Channel
      10. 8.3.10 ADC Transfer Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Interface
        1. 8.4.1.1 Digital Pin Description
          1. 8.4.1.1.1 CS (Input)
          2. 8.4.1.1.2 SCLK (Input)
          3. 8.4.1.1.3 SDI (Input)
          4. 8.4.1.1.4 SDO (Output)
          5. 8.4.1.1.5 DAISY (Input)
          6. 8.4.1.1.6 RST/PD (Input)
        2. 8.4.1.2 Data Acquisition Example
        3. 8.4.1.3 Host-to-Device Connection Topologies
          1. 8.4.1.3.1 Daisy-Chain Topology
          2. 8.4.1.3.2 Star Topology
      2. 8.4.2 Device Modes
        1. 8.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 8.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 8.4.2.3 STANDBY Mode (STDBY)
        4. 8.4.2.4 Power-Down Mode (PWR_DN)
        5. 8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)
        6. 8.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 8.4.2.7 Channel Sequencing Modes
        8. 8.4.2.8 Reset Program Registers (RST)
    5. 8.5 Register Map
      1. 8.5.1 Command Register Description
      2. 8.5.2 Program Register Description
        1. 8.5.2.1 Program Register Read/Write Operation
        2. 8.5.2.2 Program Register Map
        3. 8.5.2.3 Auto-Scan Sequencing Control Registers
          1. 8.5.2.3.1 Auto-Scan Sequence Enable Register (address = 01h)
          2. 8.5.2.3.2 Channel Power Down Register (address = 02h)
        4. 8.5.2.4 Device Features Selection Control Register (address = 03h)
        5. 8.5.2.5 Range Select Registers (address = 05h (channel 0), 06h (channel 1), 07h (channel 2), 08h (channel 3), 09h (channel 4), 0Ah (channel 5), 0Bh (channel 6), 0Ch (channel 7))
      3. 8.5.3 Command Read-Back Register (address = 3Fh)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 相关链接
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AIN_nP to AIN_nGND(2) –20 20 V
AIN_nP to AIN_nGND(3) –11 11 V
AIN_nGND to GND –0.3 0.3 V
AUX_IN to GND –0.3 AVDD + 0.3 V
AVDD to GND or DVDD to GND –0.3 7 V
REFCAP to REFGND or REFIO to REFGND –0.3 5.7 V
GND to REFGND –0.3 0.3 V
Digital input pins to GND –0.3 DVDD + 0.3 V
Digital output pins to GND –0.3 DVDD + 0.3 V
Operating temperature range, TA –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AVDD = 5 V or offers a low impedance of < 30 kΩ.
(3) AVDD = floating with an impedance > 30 kΩ.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) Analog input pins (AIN_nP; AIN_nGND) –4000 4000 V
All other pins –2000 2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage 4.75 5 5.25 V
DVDD Digital supply voltage 1.65 3.3 AVDD V

7.4 Thermal Information

THERMAL METRIC(1) ADS8684, ADS8688 UNIT
TSSOP (PW)
38 PINS
RθJA Junction-to-ambient thermal resistance 68.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.9
RθJB Junction-to-board thermal resistance 30.4
ψJT Junction-to-top characterization parameter 1.3
ψJB Junction-to-board characterization parameter 29.8
RθJC(bot) Junction-to-case (bottom) thermal resistance NA
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST(1) LEVEL
ANALOG INPUTS
Full-scale input span(2)
(AIN_nP to AIN_nGND)		 Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF V A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF V A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF V A
Input range = 2.5 × VREF 0 2.5 × VREF V A
Input range = 1.25 × VREF 0 1.25 × VREF V A
AIN_nP Operating input range,
positive input		 Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF V A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF V A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF V A
Input range = 2.5 × VREF 0 2.5 × VREF V A
Input range = 1.25 × VREF 0 1.25 × VREF V A
AIN_nGND Operating input range, negative input All input ranges –0.1 0 0.1 V B
zi Input impedance At TA = 25°C 0.85 1 1.15 MΩ B
Input impedance drift 7 25 ppm/°C B
IIkg(in) Input leakage current With voltage at AIN_nP pin = VIN,
input range = ±2.5 × VREF		 VIN – 2.25
————
RIN 		µA A
With voltage at AIN_nP pin = VIN,
input range = ±1.25 × VREF		 VIN – 2.00
————
RIN 		µA A
With voltage at AIN_nP pin = VIN,
input range = ±0.625 × VREF		 VIN – 1.60
————
RIN 		µA A
With voltage at AIN_nP pin = VIN,
input range = 2.5 × VREF		 VIN – 2.50
————
RIN 		µA A
With voltage at AIN_nP pin = VIN,
input range = 1.25 × VREF		 VIN – 2.50
————
RIN 		µA A
INPUT OVERVOLTAGE PROTECTION
VOVP Overvoltage protection voltage AVDD = 5 V or offers low impedance < 30 kΩ,
all input ranges		 –20 20 V B
AVDD = floating with impedance
> 30 kΩ, all input ranges		 –11 11 V B
SYSTEM PERFORMANCE
Resolution 16 Bits A
NMC No missing codes 16 Bits A
DNL Differential nonlinearity –0.99 ±0.5 1.5 LSB(3) A
INL Integral nonlinearity(6) –2 ±0.75 2 LSB A
EG Gain error At TA = 25°C, all input ranges ±0.02 ±0.05 %FSR(4) A
Gain error matching
(channel-to-channel)		 At TA = 25°C, all input ranges ±0.02 ±0.05 %FSR A
Gain error temperature drift All input ranges ±1 ±4 ppm/°C B
EO Offset error At TA = 25°C,
input range = ±2.5 × VREF		 ±0.5 ±0.75 mV A
At TA = 25°C,
input range = ±1.25 × VREF		 ±0.5 ±1 mV A
At TA = 25°C,
input range = ±0.625 × VREF		 ±0.5 ±1.5 mV A
At TA = 25°C,
input range = 0 to 2.5 × VREF		 ±0.5 ±2 mV A
At TA = 25°C,
input range = 0 to 1.25 × VREF		 ±0.5 ±2 mV A
Offset error matching
(channel-to-channel)		 At TA = 25°C,
input range = ±2.5 × VREF		 ±0.5 ±0.75 mV A
At TA = 25°C,
input range = ±1.25 × VREF		 ±0.5 ±1 mV A
At TA = 25°C,
input range = ±0.625 × VREF		 ±0.5 ±1.5 mV A
At TA = 25°C,
input range = 0 to 2.5 × VREF		 ±0.5 ±2 mV A
At TA = 25°C,
input range = 0 to 1.25 × VREF		 ±0.5 ±2 mV A
Offset error temperature drift All input ranges ±1 ±3 ppm/°C B
SAMPLING DYNAMICS
tCONV Conversion time 850 ns A
tACQ Acquisition time 1150 ns A
fS Maximum throughput rate
without latency		 500 kSPS A
DYNAMIC CHARACTERISTICS
SNR Signal-to-noise ratio
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±2.5 × VREF 90 92 dB A
Input range = ±1.25 × VREF 89 91 dB A
Input range = ±0.625 × VREF 87.5 89 dB A
Input range = 2.5 × VREF 88.5 90.5 dB A
Input range = 1.25 × VREF 87.5 89 dB A
THD Total harmonic distortion(5)
(VIN – 0.5 dBFS at 1 kHz)		 All input ranges –102 dB B
SINAD Signal-to-noise + distortion
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±2.5 × VREF 89 91.5 dB A
Input range = ±1.25 × VREF 88.5 91 dB A
Input range = ±0.625 × VREF 87 89 dB A
Input range = 2.5 × VREF 87.5 90.5 dB A
Input range = 1.25 × VREF 87 89 dB A
SFDR Spurious-free dynamic range
(VIN – 0.5 dBFS at 1 kHz)		 All input ranges 103 dB B
Crosstalk isolation(7) Aggressor channel input is overdriven to 2 × maximum input voltage 110 dB B
Crosstalk memory(8) Aggressor channel input is overdriven to 2 × maximum input voltage 90 dB B
BW(–3 dB) Small-signal bandwidth –3 dB At TA = 25°C, all input ranges 15 kHz B
BW(–0.1 dB) –0.1 dB At TA = 25°C, all input ranges 2.5 kHz B
AUXILIARY CHANNEL
Resolution 16 Bits A
V(AUX_IN) AUX_IN voltage range (AUX_IN – AUX_GND) 0 VREF V A
Operating input range AUX_IN 0 VREF V A
AUX_GND 0 V A
Ci Input capacitance During sampling 75 pF C
During conversion 5 pF C
IIkg(in) Input leakage current 100 nA A
DNL Differential nonlinearity –0.99 ±0.6 1.5 LSB A
INL Integral nonlinearity –4 ±1.5 4 LSB A
EG(AUX) Gain error At TA = 25°C ±0.02 ±0.2 % FSR A
EO(AUX) Offset error At TA = 25°C –10 10 mV A
SNR Signal-to-noise ratio V(AUX_IN) = –0.5 dBFS at 1 kHz 87 88 dB A
THD Total harmonic distortion(5) V(AUX_IN) = –0.5 dBFS at 1 kHz –102 dB B
SINAD Signal-to-noise + distortion V(AUX_IN) = –0.5 dBFS at 1 kHz 86 88 dB A
SFDR Spurious-free dynamic range V(AUX_IN) = –0.5 dBFS at 1 kHz 102 dB B
INTERNAL REFERENCE OUTPUT
V(REFIO_INT)(9) Voltage on REFIO pin
(configured as output)		 At TA = 25°C 4.095 4.096 4.097 V A
Internal reference temperature drift 6 10 ppm/°C B
C(OUT_REFIO) Decoupling capacitor on REFIO 10 22 µF B
V(REFCAP) Reference voltage to ADC
(on REFCAP pin)		 At TA = 25°C 4.095 4.096 4.097 V A
Reference buffer output impedance 0.5 1 Ω B
Reference buffer temperature drift 0.6 1.5 ppm/°C B
C(OUT_REFCAP) Decoupling capacitor on REFCAP 10 22 μF B
Turn-on time C(OUT_REFCAP) = 22 µF
C(OUT_REFIO) = 22 µF		 15 ms B
EXTERNAL REFERENCE INPUT
VREFIO_EXT External reference voltage on REFIO (configured as input) 4.046 4.096 4.146 V C
POWER-SUPPLY REQUIREMENTS
AVDD Analog power-supply voltage Analog supply 4.75 5 5.25 V B
DVDD Digital power-supply voltage Digital supply range 1.65 3.3 AVDD V B
Digital supply range for specified performance 2.7 3.3 5.25 V B
IAVDD_DYN Analog supply current Dynamic, AVDD For ADS8688; AVDD = 5 V, fS = maximum and internal reference 13 16 mA A
For ADS8684; AVDD = 5 V, fS = maximum and internal reference 8.5 11.5 mA A
IAVDD_STC Static For ADS8688; AVDD = 5 V, device not converting and internal reference 10 12 mA A
For ADS8684; AVDD = 5 V, device not converting and internal reference 5.5 8.5 mA A
ISTDBY Power-down At AVDD = 5 V, device in STDBY mode and internal reference 3 4.5 mA A
IPWR_DN Dynamic, DVDD At AVDD = 5 V, device in PWR_DN 3 20 μA B
IDVDD_DYN Digital supply current At DVDD = 3.3 V, output = 0000h 0.5 mA A
DIGITAL INPUTS (CMOS)
VIH Digital input logic levels
DVDD > 2.1 V		 0.7 × DVDD DVDD + 0.3 V A
VIL –0.3 0.3 × DVDD V A
VIH Digital input logic levels
DVDD ≤ 2.1 V		 0.8 × DVDD DVDD + 0.3 V A
VIL –0.3 0.2 × DVDD V A
Input leakage current 100 nA A
Input pin capacitance 5 pF C
DIGITAL OUTPUTS (CMOS)
VOH Digital output logic levels IO = 500-μA source 0.8 × DVDD DVDD V A
VOL IO = 500-μA sink 0 0.2 × DVDD V A
Floating state leakage current Only for SDO 1 µA A
Internal pin capacitance 5 pF C
TEMPERATURE RANGE
TA Operating free-air temperature –40 125 °C B
(1) Test Levels: (A) Tested at final test. Over temperature limits are set by characterization and simulation. (B) Limits set by characterization and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.
(2) Ideal input span, does not include gain or offset error.
(3) LSB = least significant bit.
(4) FSR = full-scale range.
(5) Calculated on the first nine harmonics of the input frequency.
(6) This parameter is the endpoint INL, not best fit INL.
(7) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing sequence, and measuring its effect on the output of any selected channel.
(8) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, which is selected in the multiplexing sequence, and measuring its effect on the output of the next selected channel, for all combinations of input channels.
(9) Does not include the variation in voltage resulting from solder shift effects.

7.6 Timing Requirements: Serial Interface

Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), SDO load = 20 pF, and fSAMPLE = 500 kSPS, unless otherwise noted.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
TIMING SPECIFICATIONS
fS Sampling frequency fCLK = max 500 kSPS
tS ADC cycle time period fCLK = max 2 µs
fSCLK Serial clock frequency fS = max 17 MHz
tSCLK Serial clock time period fS = max 59 ns
tCONV Conversion time 850 ns
tDV_CSDO Delay time: CS falling to data enable 10 ns
tD_CKCS Delay time: last SCLK falling to CS rising 10 ns
tDZ_CSDO Delay time: CS rising to SDO going to 3-state 10 ns
TIMING REQUIREMENTS
tACQ Acquisition time 1150 ns
tPH_CK Clock high time 0.4 0.6 tSCLK
tPL_CK Clock low time 0.4 0.6 tSCLK
tPH_CS CS high time 30 ns
tSU_CSCK Setup time: CS falling to SCLK falling 30 ns
tHT_CKDO Hold time: SCLK falling to (previous) data valid on SDO 10 ns
tSU_DOCK Setup time: SDO data valid to SCLK falling 25 ns
tSU_DICK Setup time: SDI data valid to SCLK falling 5 ns
tHT_CKDI Hold time: SCLK falling to (previous) data valid on SDI 5 ns
tSU_DSYCK Setup time: DAISY data valid to SCLK falling 5 ns
tHT_CKDSY Hold time: SCLK falling to (previous) data valid on DAISY 5 ns
tim_interface_sbas582.gifFigure 1. Serial Interface Timing Diagram

7.7 Typical Characteristics

At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
C001_SBAS582.png
Figure 2. Input I-V Characteristic
C005_SBAS582.png
Figure 4. Input Impedance Variation vs Temperature
C007_SBAS582.png
Mean = 32767.8, Sigma = 0.58, Input = 0 V,
Range = ±2.5 × VREF
Figure 6. DC Histogram for Mid-Scale Inputs (±2.5 × VREF)
C009_SBAS582.png
Mean = 32767.932767.9(TBD), Sigma = 0.76, Input = 0 V,
Range = ±0.625 × VREF
Figure 8. DC Histogram for Mid-Scale Inputs (±0.625 × VREF)
C011_SBAS582.png
Mean = 32768.90, Sigma = 0.75, Input = 0.625 × VREF,
Range = 1.25 × VREF
Figure 10. DC Histogram for Mid-Scale Inputs (1.25 × VREF)
C013_SBAS582.png
All input ranges
Figure 12. DNL vs Temperature
C015_SBAS582.png
Range = ±1.25 × VREF
Figure 14. Typical INL for All Codes
C017_SBAS582.png
Range = 2.5 × VREF
Figure 16. Typical INL for All Codes
C019_SBAS582.png
Range = ±2.5 × VREF
Figure 18. INL vs Temperature (±2.5 × VREF)
C020_SBAS582.png
Range = ±0.625 × VREF
Figure 20. INL vs Temperature (±0.625 × VREF)
C022_SBAS582.png
Range = 1.25 × VREF
Figure 22. INL vs Temperature (1.25 × VREF)
C024_SBAS582.png
Range = ±2.5 × VREF
Figure 24. Typical Histogram for Offset Drift
C026_SBAS582.png
Figure 26. Gain Error vs Temperature Across Input Ranges
C028_SBAS582.png
Range = ±2.5 × VREF
Figure 28. Gain Error vs Temperature Across Channels
C030_SBAS582.png
Number of points = 64k, fIN = 1 kHz, SNR = 92.3 dB,
SINAD = 91.9 dB, THD = 101 dB, SFDR = 104 dB
Figure 30. Typical FFT Plot (±2.5 × VREF)
C032_SBAS582.png
Number of points = 64k, fIN = 1 kHz, SNR = 89.6 dB,
SINAD = 89.5 dB, THD = 106 dB, SFDR = 107 dB
Figure 32. Typical FFT Plot (±0.625 × VREF)
C034_SBAS582.png
Number of points = 64k, fIN = 1 kHz, SNR = 89.55 dB,
SINAD = 89.4 dB, THD = 104 dB, SFDR = 107 dB
Figure 34. Typical FFT Plot (1.25 × VREF)
C036_SBAS582.png
fIN = 1 kHz
Figure 36. SNR vs Temperature
C038_SBAS582.png
fIN = 1 kHz
Figure 38. SINAD vs Temperature
C040_SBAS582.png
fIN = 1 kHz
Figure 40. THD vs Temperature
C042_SBAS582.png
Figure 42. Isolation Crosstalk vs Frequency
C044_SBAS582.png
Input = 2 × maximum input voltage
Figure 44. Isolation Crosstalk vs Frequency for
Overrange Inputs
C058_SBAS582.png
Figure 46. AVDD Current vs Temperature for ADS8688
(During Sampling)
C063_SBAS582.png
Figure 48. AVDD Current vs Temperature for ADS8684
(During Sampling)
C060_SBAS582.png
Figure 50. AVDD Current vs Temperature
(Power Down)
C002_SBAS582.png
Input range = ±2.5 × VREF
Figure 3. Input Current vs Temperature
C006_SBAS582.png
Number of samples = 1160
Figure 5. Typical Distribution of Input Impedance
C008_SBAS582.png
Mean = 32768.1, Sigma = 0.63, Input = 0 V,
Range = ±1.25 × VREF
Figure 7. DC Histogram for Mid-Scale Inputs (±1.25 × VREF)
C010_SBAS582.png
Mean = 32767.75, Sigma = 0.65, Input = 1.25 × VREF,
Range = 2.5 × VREF
Figure 9. DC Histogram for Mid-Scale Inputs (2.5 × VREF)
C012_SBAS582.png
All input ranges
Figure 11. Typical DNL for All Codes
C014_SBAS582.png
Range = ±2.5 × VREF
Figure 13. Typical INL for All Codes
C016_SBAS582.png
Range = ±0.625 × VREF
Figure 15. Typical INL for All Codes
C018_SBAS582.png
Range = 1.25 × VREF
Figure 17. Typical INL for All Codes
C061_SBAS582.png
Range = ±1.25 × VREF
Figure 19. INL vs Temperature (±1.25 × VREF)
C021_SBAS582.png
Range = 2.5 × VREF
Figure 21. INL vs Temperature (2.5 × VREF)
C023_SBAS582.png
Figure 23. Offset Error vs Temperature Across Input Ranges
C025_SBAS582.png
Range = ±2.5 × VREF
Figure 25. Offset Error vs Temperature Across Channels
C027_SBAS582.png
Range = ±2.5 × VREF
Figure 27. Typical Histogram for Gain Error Drift
C029_SBAS582.png
Figure 29. Gain Error vs External Resistance (REXT)
C031_SBAS582.png
Number of points = 64k, fIN = 1 kHz, SNR = 91.4 dB,
SINAD = 91.2 dB, THD = 105 dB, SFDR = 107 dB
Figure 31. Typical FFT Plot (±1.25 × VREF)
C033_SBAS582.png
Number of points = 64k, fIN = 1 kHz, SNR = 90.93 dB,
SINAD = 90.48 dB, THD = 100 dB, SFDR = 102 dB
Figure 33. Typical FFT Plot (2.5 × VREF)
C035_SBAS582.png
Figure 35. SNR vs Input Frequency
C037_SBAS582.png
Figure 37. SINAD vs Input Frequency
C039_SBAS582.png
Figure 39. THD vs Input Frequency
C041_SBAS582.png
Figure 41. Memory Crosstalk vs Frequency
C043_SBAS582.png
Input = 2 × maximum input voltage
Figure 43. Memory Crosstalk vs Frequency for
Overrange Inputs
C057_SBAS582.png
Figure 45. AVDD Current vs Temperature for ADS8688
(fS = 500 kSPS)
C062_SBAS582.png
Figure 47. AVDD Current vs Temperature for ADS8684
(fS = 500 kSPS)
C059_SBAS582.png
Figure 49. AVDD Current vs Temperature
(STANDBY)
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