The data read from the device can be synchronized to the external clock on the SCLK pin or to an internal clock of the device by programming the configuration registers (see the Section 7.5.4 section for details).

In any data transfer frame, the contents of the internal output shift register are shifted out on the SDO-x pins. The output data for any frame (F+1) is determined by the command issued in frame F and the status of DATA_VAL[2:0] bits:

• If the DATA_VAL[2:0] bits in the DATAOUT_CTL_REG register are set to 1xxb, then the output data word for frame (F+1) contains fixed data pattern as described in the DATAOUT_CTL_REG register.
• If a valid READ command is issued in frame F, the output data word for frame (F+1) contains 8-bit register data, followed by 0's.
• If a valid READ_HWORD command is issued in frame F, the output data word for frame (F+1) contains 16-bit register data, followed by 0's.
• For all other combinations, the output data word for frame (F+1) contains the latest 18-bit conversion result. Program the DATAOUT_CTL_REG register to append various data flags to the conversion result. The data flags are appended as per following sequence:
  1. DEVICE_ADDR[3:0] bits are appended if the DEVICE_ADDR_INCL bit is set to 1
  2. AVDD ALARM FLAGS are appended if the VDD_ACTIVE_ALARM_INCL bit is set to 1
  3. INPUT ALARM FLAGS are appended if the IN_ACTIVE_ALARM_INCL bit is set to 1
  4. ADC INPUT RANGE FLAGS are appended if the RANGE_INCL bit is set to 1
  5. PARITY bits are appended if the PAR_EN bit is set to 1
  6. All the remaining bits in the 32-bit output data word are set to 0.

Table 7-6 shows the output data word with all data flags enabled.

Table 7-7 shows output data word with only some of the data flags enabled.