ZHCSFT8B December   2016  – March 2021 ADS8691 , ADS8695 , ADS8699

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 Power-Down (PD) Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics

all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V, DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ANALOG INPUTS
VINFull-scale input span(1)
(AIN_P to AIN_GND)
Input range = ±3 × VREF–12.28812.288V
Input range = ±2.5 × VREF–10.2410.24
Input range = ±1.5 × VREF–6.1446.144
Input range = ±1.25 × VREF–5.125.12
Input range = ±0.625 × VREF–2.562.56
Input range = 3 × VREF012.288
Input range = 2.5 × VREF010.24
Input range = 1.5 × VREF06.144
Input range = 1.25 × VREF05.12
AIN_POperating input rangeInput range = ±3 × VREF–12.28812.288V
Input range = ±2.5 × VREF–10.2410.24
Input range = ±1.5 × VREF–6.1446.144
Input range = ±1.25 × VREF–5.125.12
Input range = ±0.625 × VREF–2.562.56
Input range = 3 × VREF012.288
Input range = 2.5 × VREF010.24
Input range = 1.5 × VREF06.144
Input range = 1.25 × VREF05.12
AIN_GNDOperating input rangeAll input ranges–0.100.1V
RINInput impedanceAt TA = 25°CInput range = ±3 × VREF1.021.21.38
Input range = ±1.5 × VREF1.021.21.38
Input range = 3 × VREF1.021.21.38
Input range = 1.5 × VREF1.021.21.38
Input range = ±2.5 × VREF0.8511.15
Input range = ±1.25 × VREF0.8511.15
Input range = ±0.625 × VREF0.8511.15
Input range = 2.5 × VREF0.8511.15
Input range = 1.25 × VREF0.8511.15
Input impedance drift725ppm/°C
IINInput currentWith voltage at the AIN_P pin = VINInput range = ±3 × VREF(VIN – 2.5) / RINµA
Input range = ±2.5 × VREF(VIN – 2.2) / RIN
Input range = ±1.5 × VREF(VIN – 2.0) / RIN
Input range = ±1.25 × VREF(VIN – 2.0) / RIN
Input range = ±0.625 × VREF(VIN – 1.6) / RIN
Input range = 3 × VREF(VIN – 2.6) / RIN
Input range = 2.5 × VREF(VIN – 2.5) / RIN
Input range = 1.5 × VREF(VIN – 2.7) / RIN
Input range = 1.25 × VREF(VIN – 2.5) / RIN
INPUT OVERVOLTAGE PROTECTION CIRCUIT
VOVPAll input rangesAVDD = 5 V, all input ranges–2020V
AVDD = floating, all input ranges–1515
INPUT BANDWIDTH
f–3 dBSmall-signal Input bandwidth–3 dBAll input ranges15kHz
f–0.1 dB–0.1 dBAll input ranges2.5
SYSTEM PERFORMANCE
Resolution18Bits
NMCNo missing codes18Bits
DNLDifferential nonlinearity(4)All input ranges–0.9±0.61.1LSB
INLIntegral nonlinearity(4)ADS8691Input range = ±3 × VREF, ±2.5 × VREF, ±1.5 × VREF, ±1.25 × VREF–3.25±1.753.25LSB
Input range = ±0.625 × VREF–4.25±2.254.25
All unipolar ranges(9)–3.5±23.5
ADS8695, ADS8699All input ranges–3±1.53
EOOffset error(2)At TA = 25°CAll bipolar ranges(8)–1±0.21mV
All unipolar ranges(9)–2±0.22
Offset error drift with temperatureAll input ranges–3±0.753ppm/°C
EGGain error(5)At TA = 25°C, all input ranges–0.025±0.010.025%FSR
Gain error drift with temperature(6)All input ranges–5±15ppm/°C
DYNAMIC CHARACTERISTICS
SNRSignal-to-noise ratio(7)Input range = ±3 × VREF9192.5dB
Input range = ±2.5 × VREF9192.5
Input range = ±1.5 × VREF9091.5
Input range = ±1.25 × VREF9091.5
Input range = ±0.625 × VREF87.7590
Input range = 3 × VREF89.591
Input range = 2.5 × VREF89.591
Input range = 1.5 × VREF8891
Input range = 1.25 × VREF8890
THDTotal harmonic distortion(3)(7)All input ranges–110dB
SINADSignal-to-noise + distortion(7)Input range = ±3 × VREF90.992.5dB
Input range = ±2.5 × VREF90.992.5
Input range = ±1.5 × VREF89.991.5
Input range = ±1.25 × VREF89.991.5
Input range = ±0.625 × VREF87.6590
Input range = 3 × VREF89.2591
Input range = 2.5 × VREF89.2591
Input range = 1.5 × VREF87.7590
Input range = 1.25 × VREF87.7590
SFDRSpurious-free dynamic range(7)All input ranges114dB
SAMPLING DYNAMICS
tCONVConversion timeADS8691665ns
ADS86951000
ADS86995000
tACQAcquisition timeADS8691335ns
ADS86951000
ADS86995000
fcycleMaximum throughput rate
without latency
ADS86911000kSPS
ADS8695500
ADS8699100
INTERNAL REFERENCE OUTPUT
VREFIOOn the REFIO pin
(configured as an output)
At TA = 25°C4.0954.0964.097V
dVREFIO/dTAInternal reference temperature drift47ppm/°C
COUT_REFIODecoupling capacitor on REFIO pin4.7µF
VREFCAPReference voltage to the ADC
(on the REFCAP pin)
At TA = 25°C4.0954.0964.097V
REFCAP temperature drift0.52ppm/°C
COUT_REFCAPDecoupling capacitor on REFCAP pin10μF
Turn-on timeCOUT_REFCAP = 10 µF, COUT_REFIO = 10 µF20ms
EXTERNAL REFERENCE INPUT
VREFIO_EXTExternal reference voltage on REFIOREFIO pin configured as an input4.0464.0964.146V
AVDD COMPARATOR
VTH_HIGHHigh threshold voltage5.3V
VTH_LOWLow threshold voltage4.7V
POWER-SUPPLY REQUIREMENTS
AVDDAnalog power-supply voltage4.7555.25V
DVDDDigital power-supply voltageOperating range1.653.3AVDD
Supply range for specified performance2.73.3AVDD
IAVDD_DYNAnalog supply current,
device converting at maximum throughput
Internal referenceADS86918.210.5mA
ADS86955.67.25
ADS869945
External referenceADS86917.08.75
ADS86954.45.5
ADS86992.73.25
IAVDD_STCAnalog supply current,
device not converting
Internal referenceADS86914.76.25mA
ADS8695, ADS86993.54.7
External referenceADS86913.54.5
ADS8695, ADS86992.33
IAVDD_STDBYAnalog supply current,
device in STANDBY mode
Internal reference2.8mA
External reference1.6
IAVDD_PDAnalog supply current,
device in PD mode
Internal reference10μA
External reference10
IDVDD_DYNDigital supply current,
maximum throughput
0.20.25mA
IDVDD_STDBYDigital supply current,
device in STANDBY mode
1μA
IDVDD_PDDigital supply current,
device in PD mode
1μA
DIGITAL INPUTS (CMOS)
VIHDigital high input voltage logic levelDVDD > 2.35 V0.7 × DVDDDVDD + 0.3V
DVDD ≤ 2.35 V0.8 × DVDDDVDD + 0.3
VILDigital low input voltage logic levelDVDD > 2.35 V–0.30.3 × DVDDV
DVDD ≤ 2.35 V–0.30.2 × DVDD
Input leakage current100nA
Input pin capacitance5pF
DIGITAL OUTPUTS (CMOS)
VOHDigital high output voltage logic levelIO = 500-μA source0.8 × DVDDDVDDV
VOLDigital low output voltage logic levelIO = 500-μA sink00.2 × DVDDV
Floating state leakage currentOnly for digital output pins1µA
Internal pin capacitance5pF
TEMPERATURE RANGE
TAOperating free-air temperature–40125°C
Ideal input span, does not include gain or offset error.
Measured relative to actual measured reference.
Calculated on the first nine harmonics of the input frequency.
This specification indicates the endpoint INL, not best-fit INL.
Excludes internal reference accuracy error.
Excludes internal reference temperature drift.
All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with a 1-kHz input signal 0.25 dB below full-scale, unless otherwise specified.
Bipolar ranges are ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V.
Unipolar ranges are 0 V–12.288 V, 0 V–10.24 V, 0 V–6.144 V, and 0 V–5.12 V.