ZHCSDW2 July   2015 ADS8694 , ADS8698

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
      2. 8.3.2  Analog Input Impedance
      3. 8.3.3  Input Overvoltage Protection Circuit
      4. 8.3.4  Programmable Gain Amplifier (PGA)
      5. 8.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 8.3.6  ADC Driver
      7. 8.3.7  Multiplexer (MUX)
      8. 8.3.8  Reference
        1. 8.3.8.1 Internal Reference
        2. 8.3.8.2 External Reference
      9. 8.3.9  Auxiliary Channel
        1. 8.3.9.1 Input Driver for the AUX Channel
      10. 8.3.10 ADC Transfer Function
      11. 8.3.11 Alarm Feature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Interface
        1. 8.4.1.1 Digital Pin Description
          1. 8.4.1.1.1 CS (Input)
          2. 8.4.1.1.2 SCLK (Input)
          3. 8.4.1.1.3 SDI (Input)
          4. 8.4.1.1.4 SDO (Output)
          5. 8.4.1.1.5 DAISY (Input)
          6. 8.4.1.1.6 RST/PD (Input)
        2. 8.4.1.2 Data Acquisition Example
        3. 8.4.1.3 Host-to-Device Connection Topologies
          1. 8.4.1.3.1 Daisy-Chain Topology
          2. 8.4.1.3.2 Star Topology
      2. 8.4.2 Device Modes
        1. 8.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 8.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 8.4.2.3 STANDBY Mode (STDBY)
        4. 8.4.2.4 Power-Down Mode (PWR_DN)
        5. 8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)
        6. 8.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 8.4.2.7 Channel Sequencing Modes
        8. 8.4.2.8 Reset Program Registers (RST)
    5. 8.5 Register Maps
      1. 8.5.1 Command Register Description
      2. 8.5.2 Program Register Description
        1. 8.5.2.1 Program Register Read/Write Operation
        2. 8.5.2.2 Program Register Map
        3. 8.5.2.3 Program Register Descriptions
          1. 8.5.2.3.1 Auto-Scan Sequencing Control Registers
            1. 8.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)
            2. 8.5.2.3.1.2 Channel Power Down Register (address = 02h)
          2. 8.5.2.3.2 Device Features Selection Control Register (address = 03h)
          3. 8.5.2.3.3 Range Select Registers (addresses 05h-0Ch)
          4. 8.5.2.3.4 Alarm Flag Registers (Read-Only)
            1. 8.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)
            2. 8.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          5. 8.5.2.3.5 Alarm Threshold Setting Registers
          6. 8.5.2.3.6 Command Read-Back Register (address = 3Fh)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 18-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AIN_nP, AIN_nGND to GND(2) –20 20 V
AIN_nP, AIN_nGND to GND(3) –11 11 V
AUX_GND to GND –0.3 0.3 V
AUX_IN to GND –0.3 AVDD + 0.3 V
AVDD to GND or DVDD to GND –0.3 7 V
REFCAP to REFGND or REFIO to REFGND –0.3 5.7 V
GND to REFGND –0.3 0.3 V
Digital input pins to GND –0.3 DVDD + 0.3 V
Digital output pins to GND –0.3 DVDD + 0.3 V
Operating temperature, TA –40 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AVDD = 5 V or offers a low impedance of < 30 kΩ.
(3) AVDD = floating with an impedance > 30 kΩ.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Analog input pins (AIN_nP; AIN_nGND) ±4000 V
All other pins ±2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage 4.75 5 5.25 V
DVDD Digital supply voltage 1.65 3.3 AVDD V

7.4 Thermal Information

THERMAL METRIC(1) ADS8694, ADS8698 UNIT
DBT (TSSOP)
38 PINS
RθJA Junction-to-ambient thermal resistance 68.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.9 °C/W
RθJB Junction-to-board thermal resistance 30.4 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 29.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance NA °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
ANALOG INPUTS
Full-scale input span(2)
(AIN_nP to AIN_nGND)		 Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF V A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF A
Input range = 2.5 × VREF 0 2.5 × VREF A
Input range = 1.25 × VREF 0 1.25 × VREF A
AIN_nP Operating input range,
positive input		 Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF V A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF A
Input range = 2.5 × VREF 0 2.5 × VREF A
Input range = 1.25 × VREF 0 1.25 × VREF A
AIN_nGND Operating input range,
negative input		 All input ranges –0.1 0 0.1 V B
zi Input impedance At TA = 25°C,
all input ranges		 0.85 1 1.15 MΩ B
Input impedance drift All input ranges 7 25 ppm/°C B
IIkg(in) Input leakage current With voltage at AIN_nP pin = VIN,
input range = ±2.5 × VREF		 VIN – 2.25
————
RIN 		µA A
With voltage at AIN_nP pin = VIN,
input range = ±1.25 × VREF		 VIN – 2.00
————
RIN 		A
With voltage at AIN_nP pin = VIN,
input range = ±0.625 × VREF		 VIN – 1.60
————
RIN 		A
With voltage at AIN_nP pin = VIN,
input range = 2.5 × VREF		 VIN – 2.50
————
RIN 		A
With voltage at AIN_nP pin = VIN,
input range = 1.25 × VREF		 VIN – 2.50
————
RIN 		A
INPUT OVERVOLTAGE PROTECTION
VOVP Overvoltage protection voltage AVDD = 5 V or offers low impedance < 30 kΩ, all input ranges –20 20 V B
AVDD = floating with impedance
> 30 kΩ, all input ranges		 –11 11 B
SYSTEM PERFORMANCE
Resolution 18 Bits A
NMC No missing codes 18 Bits A
DNL Differential nonlinearity –0.99 ±0.5 2 LSB(3) A
INL Integral nonlinearity(6) –5 ±1.5 5 LSB A
EG Gain error At TA = 25°C, all input ranges ±0.02 ±0.05 %FSR(4) A
Gain error matching
(channel-to-channel)		 At TA = 25°C, all input ranges ±0.02 ±0.05 %FSR A
Gain error temperature drift All input ranges 1 4 ppm/°C B
EO Offset error At TA = 25°C,
input range = ±2.5 × VREF(10)		 ±0.5 ±1 mV A
At TA = 25°C,
input range = ±1.25 × VREF		 ±0.5 ±1 A
At TA = 25°C,
input range = ±0.625 × VREF		 ±0.5 ±1.5 A
At TA = 25°C,
input range = 0 to 2.5 × VREF		 ±0.5 ±2 A
At TA = 25°C,
input range = 0 to 1.25 × VREF		 ±0.5 ±2 A
Offset error matching
(channel-to-channel)		 At TA = 25°C,
input range = ±2.5 × VREF(10)		 ±0.5 ±1 mV A
At TA = 25°C,
input range = ±1.25 × VREF		 ±0.5 ±1 A
At TA = 25°C,
input range = ±0.625 × VREF		 ±0.5 ±1.5 A
At TA = 25°C,
input range = 0 to 2.5 × VREF		 ±0.5 ±2 A
At TA = 25°C,
input range = 0 to 1.25 × VREF		 ±0.5 ±2 A
Offset error temperature drift All input ranges 1 3 ppm/°C B
SAMPLING DYNAMICS
tCONV Conversion time 825 ns A
tACQ Acquisition time 1175 ns A
fS Maximum throughput rate
without latency		 500 kSPS A
DYNAMIC CHARACTERISTICS
SNR Signal-to-noise ratio
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±2.5 × VREF 91 93.5 dB A
Input range = ±1.25 × VREF 90 92.5 A
Input range = ±0.625 × VREF 88 90.5 A
Input range = 2.5 × VREF 89.5 92 A
Input range = 1.25 × VREF 88 90.5 A
THD Total harmonic distortion(5)
(VIN – 0.5 dBFS at 1 kHz)		 All input ranges –105 dB B
SINAD Signal-to-noise ratio
(VIN – 0.5 dBFS at 1 kHz)		 Input range = ±2.5 × VREF 90 93.5 dB A
Input range = ±1.25 × VREF 89 92.3 A
Input range = ±0.625 × VREF 87.5 90.5 A
Input range = 2.5 × VREF 88.5 91.8 A
Input range = 1.25 × VREF 87.5 90.2 A
SFDR Spurious-free dynamic range
(VIN – 0.5 dBFS at 1 kHz)		 All input ranges 106 dB B
Crosstalk isolation(7) Aggressor channel input overdriven to 2 × maximum input voltage 110 dB B
Crosstalk memory(8) Aggressor channel input overdriven to 2 × maximum input voltage 90 dB B
BW(–3 dB) Small-signal bandwidth, –3 dB At TA = 25°C, all input ranges 15 kHz B
BW(–0.1 dB) Small-signal bandwidth, –0.1 dB At TA = 25°C, all input ranges 2.5 kHz B
AUXILIARY CHANNEL
Resolution 16 Bits A
V(AUX_IN) AUX_IN voltage range (AUX_IN – AUX_GND) 0 VREF V A
Operating input range AUX_IN 0 VREF V A
AUX_GND 0 V A
Ci Input capacitance During sampling 75 pF C
During conversion 5 pF C
IIkg(in) Input leakage current 100 nA A
DNL Differential nonlinearity –0.99 ±0.6 1.5 LSB A
INL Integral nonlinearity –4 ±1.5 4 LSB A
EG(AUX) Gain error At TA = 25°C ±0.02 ±0.2 %FSR A
EO(AUX) Offset error At TA = 25°C –5 5 mV A
SNR Signal-to-noise ratio V(AUX_IN) = –0.5 dBFS at 1 kHz 87 89 dB A
THD Total harmonic distortion(5) V(AUX_IN) = –0.5 dBFS at 1 kHz –102 dB B
SINAD Signal-to-noise + distortion V(AUX_IN) = –0.5 dBFS at 1 kHz 86 88.5 dB A
SFDR Spurious-free dynamic range V(AUX_IN) = –0.5 dBFS at 1 kHz 103 dB B
INTERNAL REFERENCE OUTPUT
V(REFIO_INT)(9) Voltage on REFIO pin
(configured as output)		 At TA = 25°C 4.095 4.096 4.097 V A
Internal reference temperature drift 6 10 ppm/°C B
C(OUT_REFIO) Decoupling capacitor on REFIO 10 22 µF B
V(REFCAP) Reference voltage to ADC
(on REFCAP pin)		 At TA = 25°C 4.095 4.096 4.097 V A
Reference buffer output impedance 0.5 1 Ω B
Reference buffer temperature drift 0.6 1.5 ppm/°C B
C(OUT_REFCAP) Decoupling capacitor on REFCAP 10 22 μF B
Turn-on time C(OUT_REFCAP) = 22 µF,
C(OUT_REFIO) = 22 µF		 15 ms B
EXTERNAL REFERENCE INPUT
VREFIO_EXT External reference voltage on REFIO (configured as input) 4.046 4.096 4.146 V C
POWER-SUPPLY REQUIREMENTS
AVDD Analog power-supply voltage Analog supply 4.75 5 5.25 V B
DVDD Digital power-supply voltage Digital supply range 1.65 3.3 AVDD V B
Digital supply range for specified performance 2.7 3.3 5.25 B
IAVDD_DYN Analog supply current Dynamic, AVDD For the ADS8698; AVDD = 5 V, fS = maximum and internal reference 13 16 mA A
For the ADS8694; AVDD = 5 V, fS = maximum and internal reference 8.5 11.5 A
IAVDD_STC Static For the ADS8698; AVDD = 5 V, device not converting and internal reference 10 12 mA A
For the ADS8694; AVDD = 5 V, device not converting and internal reference 5.5 8.5 A
ISTDBY Standby At AVDD = 5 V, device in STDBY mode and internal reference 3 4.5 mA A
IPWR_DN Power-down At AVDD = 5 V, device in PWR_DN 3 20 μA B
IDVDD_DYN Digital supply current At DVDD = 3.3 V, output = 0000h 0.5 mA A
DIGITAL INPUTS (CMOS)
VIH Digital input logic levels
DVDD > 2.1 V		 0.7 × DVDD DVDD + 0.3 V A
VIL –0.3 0.3 × DVDD A
VIH Digital input logic levels
DVDD ≤ 2.1 V		 0.8 × DVDD DVDD + 0.3 V A
VIL –0.3 0.2 × DVDD A
Input leakage current 100 nA A
Input pin capacitance 5 pF C
DIGITAL OUTPUTS (CMOS)
VOH Digital output logic levels IO = 500-μA source 0.8 × DVDD DVDD V A
VOL IO = 500-μA sink 0 0.2 × DVDD A
Floating state leakage current Only for SDO 1 µA A
Internal pin capacitance 5 pF C
TEMPERATURE RANGE
TA Operating free-air temperature –40 125 °C B
(1) Test Levels: (A) Tested at final test. Over temperature limits are set by characterization and simulation. (B) Limits set by characterization and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.
(2) Ideal input span, does not include gain or offset error.
(3) LSB = least significant bit.
(4) FSR = full-scale range.
(5) Calculated on the first nine harmonics of the input frequency.
(6) This parameter is the endpoint INL, not best-fit INL.
(7) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing sequence, and measuring its effect on the output of any selected channel.
(8) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel that is selected in the multiplexing sequence, and measuring its effect on the output of the next selected channel for all combinations of input channels.
(9) Does not include the variation in voltage resulting from solder-shift and long-term effects.
(10) Does not include the shift in offset over time.

7.6 Timing Requirements: Serial Interface

Minimum and maximum specifications are at TA = –40°C to 125°C. Typical specifications are at TA = 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), SDO load = 20 pF, and fSAMPLE = 500 kSPS, unless otherwise noted.
MIN TYP MAX UNIT
TIMING SPECIFICATIONS
fS Sampling frequency (fCLK = max) 500 kSPS
tS ADC cycle time period (fCLK = max) 2 µs
fSCLK Serial clock frequency (fS = max) 18 MHz
tSCLK Serial clock time period (fS = max) 56 ns
tCONV Conversion time 825 ns
tDZ_CSDO Delay time: CS falling to data enable 10 ns
tD_CKCS Delay time: last SCLK falling to CS rising 10 ns
tDZ_CSDO Delay time: CS rising to SDO going to 3-state 10 ns
TIMING REQUIREMENTS
tACQ Acquisition time 1175 ns
tPH_CK Clock high time 0.4 0.6 tSCLK
tPL_CK Clock low time 0.4 0.6 tSCLK
tPH_CS CS high time 30 ns
tSU_CSCK Setup time: CS falling to SCLK falling 30 ns
tHT_CKDO Hold time: SCLK falling to (previous) data valid on SDO 10 ns
tSU_DOCK Setup time: SDO data valid to SCLK falling 25 ns
tSU_DICK Setup time: SDI data valid to SCLK falling 5 ns
tHT_CKDI Hold time: SCLK falling to (previous) data valid on SDI 5 ns
tSU_DSYCK Setup time: DAISY data valid to SCLK falling 5 ns
tHT_CKDSY Hold time: SCLK falling to (previous) data valid on DAISY 5 ns
ADS8694 ADS8698 tim_interface_sbas686.gifFigure 1. Serial Interface Timing Diagram

7.7 Typical Characteristics

At TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS, unless otherwise noted.
ADS8694 ADS8698 C001_SBAS686.png
Figure 2. Input I-V Characteristic
ADS8694 ADS8698 C005_SBAS686.png
Figure 4. Input Impedance Variation vs Temperature
ADS8694 ADS8698 C007_SBAS686.png
Mean = 131072.3, sigma = 2.02, input = 0 V,
range = ±2.5 × VREF
Figure 6. DC Histogram for Mid-Scale Inputs (±2.5 × VREF)
ADS8694 ADS8698 C009_SBAS686.png
Mean = 131072.3, sigma = 2.76, input = 0 V,
range = ±0.625 × VREF
Figure 8. DC Histogram for Mid-Scale Inputs (±0.625 × VREF)
ADS8694 ADS8698 C011_SBAS686.png
Mean = 131072.3, sigma = 2.71, input = 0.625 × VREF,
range = 1.25 × VREF
Figure 10. DC Histogram for Mid-Scale Inputs
(1.25 × VREF)
ADS8694 ADS8698 C013_SBAS686.png
All input ranges
Figure 12. DNL vs Temperature
ADS8694 ADS8698 C015_SBAS686.png
Range = ±1.25 × VREF
Figure 14. Typical INL for All Codes
ADS8694 ADS8698 C017_SBAS686.png
Range = 2.5 × VREF
Figure 16. Typical INL for All Codes
ADS8694 ADS8698 C019_SBAS686.png
Range = ±2.5 × VREF
Figure 18. INL vs Temperature (±2.5 × VREF)
ADS8694 ADS8698 C020_SBAS686.png
Range = ±0.625 × VREF
Figure 20. INL vs Temperature (±0.625 × VREF)
ADS8694 ADS8698 C022_SBAS686.png
Range = 1.25 × VREF
Figure 22. INL vs Temperature (1.25 × VREF)
ADS8694 ADS8698 C025_SBAS686.png
Range = ±2.5 × VREF
Figure 24. Typical Histogram for Offset Drift
ADS8694 ADS8698 C027_SBAS686.png
Figure 26. Gain Error vs Temperature Across Input Ranges
ADS8694 ADS8698 C029_SBAS686.png
Range = ±2.5 × VREF
Figure 28. Gain Error vs Temperature Across Channels
ADS8694 ADS8698 C031_SBAS686.png
Number of points = 64k, fIN = 1 kHz, SNR = 93.48 dB,
SINAD = 93.29 dB, THD = 106 dB, SFDR = 108 dB
Figure 30. Typical FFT Plot (±2.5 × VREF)
ADS8694 ADS8698 C033_SBAS686.png
Number of points = 64k, fIN = 1 kHz, SNR = 90.6dB,
SINAD = 90.45dB, THD = –106dB, SFDR = 109 dB
Figure 32. Typical FFT Plot (±0.625 × VREF)
ADS8694 ADS8698 C035_SBAS686.png
Number of points = 64k, fIN = 1 kHz, SNR = 90.55 dB,
SINAD = 90.3dB, THD = –106 dB, SFDR = 108 dB
Figure 34. Typical FFT Plot (1.25 × VREF)
ADS8694 ADS8698 C037_SBAS686.png
fIN = 1 kHz
Figure 36. SNR vs Temperature
ADS8694 ADS8698 C039_SBAS686.png
fIN = 1 kHz
Figure 38. SINAD vs Temperature
ADS8694 ADS8698 C041_SBAS686.png
fIN = 1 kHz
Figure 40. THD vs Temperature
ADS8694 ADS8698 C043_SBAS686.png
Figure 42. Isolation Crosstalk vs Frequency
ADS8694 ADS8698 C045_SBAS686.png
Input = 2 × maximum input voltage
Figure 44. Isolation Crosstalk vs Frequency for
Overrange Inputs
ADS8694 ADS8698 C059_SBAS686.png
Figure 46. AVDD Current vs Temperature for the ADS8698
(During Sampling)
ADS8694 ADS8698 C063_SBAS686.png
Figure 48. AVDD Current vs Temperature for the ADS8694
(During Sampling)
ADS8694 ADS8698 C077_SBAS680.png
Figure 50. AVDD Current vs Temperature
(Power Down)
ADS8694 ADS8698 C002_SBAS686.png
Input range = ±2.5 × VREF
Figure 3. Input Current vs Temperature
ADS8694 ADS8698 C006_SBAS686.png
Number of samples = 1160
Figure 5. Typical Distribution of Input Impedance
ADS8694 ADS8698 C008_SBAS686.png
Mean = 131072.3, sigma = 2.21, input = 0 V,
range = ±1.25 × VREF
Figure 7. DC Histogram for Mid-Scale Inputs (±1.25 × VREF)
ADS8694 ADS8698 C010_SBAS686.png
Mean = 131072.3, sigma = 2.42, input = 1.25 × VREF,
range = 2.5 × VREF
Figure 9. DC Histogram for Mid-Scale Inputs (2.5 × VREF)
ADS8694 ADS8698 C012_SBAS686.png
All input ranges
Figure 11. Typical DNL for All Codes
ADS8694 ADS8698 C014_SBAS686.png
Range = ±2.5 × VREF
Figure 13. Typical INL for All Codes
ADS8694 ADS8698 C016_SBAS686.png
Range = ±0.625 × VREF
Figure 15. Typical INL for All Codes
ADS8694 ADS8698 C018_SBAS686.png
Range = 1.25 × VREF
Figure 17. Typical INL for All Codes
ADS8694 ADS8698 C020_SBAS686.png
Range = ±1.25 × VREF
Figure 19. INL vs Temperature (±1.25 × VREF)
ADS8694 ADS8698 C021_SBAS686.png
Range = 2.5 × VREF
Figure 21. INL vs Temperature (2.5 × VREF)
ADS8694 ADS8698 C024_SBAS686.png
Figure 23. Offset Error vs
Temperature Across Input Ranges
ADS8694 ADS8698 C026_SBAS686.png
Range = ±2.5 × VREF
Figure 25. Offset Error vs Temperature Across Channels
ADS8694 ADS8698 C028_SBAS686.png
Range = ±2.5 × VREF
Figure 27. Typical Histogram for Gain Error Drift
ADS8694 ADS8698 C030_SBAS686.png
Figure 29. Gain Error vs External Resistance (REXT)
ADS8694 ADS8698 C032_SBAS686.png
Number of points = 64k, fIN = 1 kHz, SNR = 92.4dB,
SINAD = 92.2dB, THD = 107 dB, SFDR = 110 dB
Figure 31. Typical FFT Plot (±1.25 × VREF)
ADS8694 ADS8698 C034_SBAS686.png
Number of points = 64k, fIN = 1 kHz, SNR = 91.83 dB,
SINAD = 91.73 dB, THD = –108 dB, SFDR = 107 dB
Figure 33. Typical FFT Plot (2.5 × VREF)
ADS8694 ADS8698 C036_SBAS686.png
Figure 35. SNR vs Input Frequency
ADS8694 ADS8698 C038_SBAS686.png
Figure 37. SINAD vs Input Frequency
ADS8694 ADS8698 C040_SBAS686.png
Figure 39. THD vs Input Frequency
ADS8694 ADS8698 C042_SBAS686.png
Figure 41. Memory Crosstalk vs Frequency
ADS8694 ADS8698 C044_SBAS686.png
Input = 2 × maximum input voltage
Figure 43. Memory Crosstalk vs Frequency for
Overrange Inputs
ADS8694 ADS8698 C058_SBAS686.png
Figure 45. AVDD Current vs Temperature for the ADS8698
(fS = 500 kSPS)
ADS8694 ADS8698 C062_SBAS686.png
Figure 47. AVDD Current vs Temperature for the ADS8694
(fS = 500 kSPS)
ADS8694 ADS8698 C060_SBAS686.png
Figure 49. AVDD Current vs Temperature
(STANDBY)
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |