10.2.3.2 Detailed Design Procedure

The data acquisition circuit shown in Figure 65 is optimized for using the ADS8862 at a reduced throughput of 10 kSPS

In order to save power, this circuit is operated on a single 3.3-V supply. The circuit uses the OPA333 with a maximum quiescent current of 28 µA in order to drive the ADC input. The input amplifier is configured in a modified unity-gain buffer configuration. The filter capacitor at the ADC inputs attenuates the sampling charge injection noise from the ADC but effects the stability of the input amplifiers by degrading the phase margin. This attenuation requires a series isolation resistor to maintain amplifier stability. The value of the series resistor is directly proportional to the open-loop output impedance of the driving amplifier to maintain stability, which is high (in the order of kΩ) in the case of low-power amplifiers such as the OPA333. Therefore, a high value of 1 kΩ is selected for the series resistor at the ADC inputs. However, this series resistor creates an additional voltage drop in the signal path, thereby leading to linearity and distortion issues. The dual-feedback configuration used in Figure 65 corrects for this additional voltage drop and maintains system performance at ultralow-power consumption.