米6体育平台手机版

ZHCSBG8B May 2013 – March 2019 ADS8864

PRODUCTION DATA.

all specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
t_ACQ	Acquisition time	1200		ns
t_conv	Conversion time	500	1300	ns
1/f_sample	Time between conversions	2500		ns
t_su-CK-CNV	Setup time: SCLK valid to CONVST rising edge	5		ns
t_h-CK-CNV	Hold time: SCLK valid from CONVST rising edge	5		ns
t_su-DI-CNV	Setup time: DIN low to CONVST rising edge (see Figure 2)	7.5		ns
t_h-DI-CNV	Hold time: DIN low from CONVST rising edge (see Figure 61)	0		ns
t_su-DI-CK	Setup time: DIN valid to SCLK falling edge	1.5		ns

Figure 1. 3-Wire Operation: CONVST Functions as Chip Select

NOTE: Figure 1 shows the timing diagram for the 3-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 3-Wire Operation table are also applicable for the 3-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.

Figure 2. 4-Wire Operation: DIN Functions as Chip Select

NOTE: Figure 2 shows the timing diagram for the 4-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 4-Wire Operation table are also applicable for the 4-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.

Figure 3. Daisy-Chain Operation: Two Devices

NOTE: Figure 3 shows the timing diagram for the Daisy-Chain Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: Daisy-Chain table are also applicable for the Daisy-Chain Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.