米6体育平台手机版

ZHCS147D May 2013 – August 2015

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DGS|10
- MPDS035C
DRC|10
- MPDS117L

散热焊盘机械数据 (封装 | 引脚)

DRC|10
- QFND213I

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
AINP to GND or AINN to GND		–0.3	REF + 0.3	V
AVDD to GND or DVDD to GND		–0.3	4	V
REF to GND		–0.3	5.7	V
Digital input voltage to GND		–0.3	DVDD + 0.3	V
Digital output to GND		–0.3	DVDD + 0.3	V
Operating temperature, T_A	ADS8881C	0	70	°C
Operating temperature, T_A	ADS8881I	–40	85	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		NOM	UNIT
AVDD	Analog power supply	3	V
DVDD	Digital power supply	3	V
V_REF	Reference voltage	5	V

7.4 Thermal Information

THERMAL METRIC		ADS8881		UNIT
		DGS (VSSOP)	DRC (VSON)
		10 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance	151.9	111.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	45.4	46.4	°C/W
R_θJB	Junction-to-board thermal resistance	72.2	45.9	°C/W
ψ_JT	Junction-to-top characterization parameter	3.3	3.5	°C/W
ψ_JB	Junction-to-board characterization parameter	70.9	45.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	N/A	°C/W

7.5 Electrical Characteristics

All minimum and maximum specifications are at AVDD = 3 V, DVDD = 3 V, V_REF = 5 V, V_CM = V_REF / 2 V,
and f_SAMPLE = 1 MSPS, over the operating free-air temperature range, unless otherwise noted.
Typical specifications are at T_A = 25°C, AVDD = 3 V, and DVDD = 3 V.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
	Full-scale input span⁽¹⁾⁽⁸⁾		AINP – AINN	–V_REF		V_REF	V
	Operating input range⁽¹⁾⁽⁸⁾		AINP	–0.1		V_REF + 0.1	V
	Operating input range⁽¹⁾⁽⁸⁾		AINN	–0.1		V_REF + 0.1	V
V_CM	Input common-mode range			0	V_REF / 2	V_REF	V
C_I	Input capacitance		AINP and AINN terminal to GND		59		pF
EXTERNAL REFERENCE INPUT
V_REF	Input range		ADS8881C	3		5	V
V_REF	Input range		ADS8881I	2.5		5	V
	Reference input current		During conversion, 1-MHz sample rate, mid-code		300		μA
	Reference leakage current				250		nA
C_REF	Decoupling capacitor at the REF input			10	22		µF
	Input leakage current		During acquisition for dc input		5		nA
SYSTEM PERFORMANCE
	Resolution				18		Bits
NMC	No missing codes			18			Bits
DNL	Differential linearity		ADS8881C	–0.99	±0.6	1	LSB⁽²⁾
DNL	Differential linearity		ADS8881I	–0.99	±0.7	1.5	LSB⁽²⁾
INL	Integral linearity⁽⁵⁾		ADS8881C	–2	±1.2	2	LSB⁽²⁾
INL	Integral linearity⁽⁵⁾		ADS8881I	–3	±1.5	3	LSB⁽²⁾
E_O	Offset error⁽³⁾			–4	±1	4	mV
	Offset error drift with temperature				±1.5		µV/°C
E_G	Gain error			–0.01	±0.005	0.01	%FSR
	Gain error drift with temperature				±0.15		ppm/°C
CMRR	Common-mode rejection ratio			90	100		dB
PSRR	Power-supply rejection ratio		At mid-code		80		dB
	Transition noise				0.7		LSB
SAMPLING DYNAMICS
t_conv	Conversion time			500		710	ns
t_ACQ	Acquisition time			290			ns
	Maximum throughput rate with or without latency					1000	kHz
	Aperture delay				4		ns
	Aperture jitter, RMS				5		ps
	Step response		Settling to 18-bit accuracy		290		ns
	Overvoltage recovery		Settling to 18-bit accuracy		290		ns
DYNAMIC CHARACTERISTICS
SINAD	Signal-to-noise + distortion⁽⁷⁾		At 1 kHz, V_REF = 5 V	98	99.9		dB
			At 10 kHz, V_REF = 5 V		98.7
			At 100 kHz, V_REF = 5 V		93.3
SNR	Signal-to-noise ratio⁽⁷⁾		At 1 kHz, V_REF = 5 V	98.5	100		dB
			At 10 kHz, V_REF = 5 V		99.5
			At 100 kHz, V_REF = 5 V		93.5
THD	Total harmonic distortion⁽⁷⁾⁽⁴⁾		At 1 kHz, V_REF = 5 V		–115		dB
			At 10 kHz, V_REF = 5 V		–112
			At 100 kHz, V_REF = 5 V		–102
SFDR	Spurious-free dynamic range⁽⁷⁾		At 1 kHz, V_REF = 5 V		115		dB
			At 10 kHz, V_REF = 5 V		112
			At 100 kHz, V_REF = 5 V		102
BW_–3dB	–3-dB small-signal bandwidth				30		MHz
POWER-SUPPLY REQUIREMENTS
	Power-supply voltage	AVDD	Analog supply	2.7	3	3.6	V
		DVDD	Digital supply range for SCLK > 40 MHz	2.7	3	3.6
		DVDD	Digital supply range for SCLK < 40 MHz	1.65	1.8	3.6
	Supply current	AVDD	1-MHz sample rate, AVDD = 3 V		1.8	2.4	mA
P_VA	Power dissipation		1-MHz sample rate, AVDD = 3 V		5.5	7.2	mW
			100-kHz sample rate, AVDD = 3 V		0.55		mW
			10-kHz sample rate, AVDD = 3 V		55		μW
IA_PD	Device power-down current⁽⁶⁾				50		nA
DIGITAL INPUTS: LOGIC FAMILY (CMOS)
V_IH	High-level input voltage		1.65 V < DVDD < 2.3 V	0.8 × DVDD		DVDD + 0.3	V
V_IH	High-level input voltage		2.3 V < DVDD < 3.6 V	0.7 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		1.65 V < DVDD < 2.3 V	–0.3		0.2 × DVDD	V
V_IL	Low-level input voltage		2.3 V < DVDD < 3.6 V	–0.3		0.3 × DVDD	V
I_LK	Digital input leakage current				±10	±100	nA
DIGITAL OUTPUTS: LOGIC FAMILY (CMOS)
V_OH	High-level output voltage		I_O = 500-μA source, C_LOAD = 20 pF	0.8 × DVDD		DVDD	V
V_OL	Low-level output voltage		I_O = 500-μA sink, C_LOAD = 20 pF	0		0.2 × DVDD	V
TEMPERATURE RANGE
T_A	Operating free-air temperature		ADS8881C	0		70	°C
T_A	Operating free-air temperature		ADS8881I	–40		85	°C

(1) Ideal input span, does not include gain or offset error.

(2) LSB = least significant bit. 1 LSB at 18-bits is approximately 3.8 ppm.

(3) Measured relative to actual measured reference.

(4) Calculated on the first nine harmonics of the input frequency.

(5) This parameter is the endpoint INL, not best-fit.

(6) The device automatically enters a power-down state at the end of every conversion, and remains in power-down during the acquisition phase.

(7) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.

(8) Specified for V_CM = V_REF / 2; see the Analog Input section for the effect of V_CM on the full-scale input range.

7.6 Timing Requirements: 3-Wire Operation

All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted.

			MIN	MAX	UNIT
t_ACQ	Acquisition time		290		ns
t_conv	Conversion time	T_A in the range –40°C to 85°C	500	710	ns
t_conv	Conversion time	T_A in the range 0°C to 70°C	500	700	ns
t_conv	Conversion time		500		ns
1/f_sample	Time between conversions		1000		ns
t_wh-CNV	Pulse duration: CONVST high		10		ns
f_SCLK	SCLK frequency			70	MHz
t_SCLK	SCLK period		14.3		ns
t_clkl	SCLK low time		0.45	0.55	t_SCLK
t_clkh	SCLK high time		0.45	0.55	t_SCLK
t_h-CK-DO	SCLK falling edge to current data invalid		3		ns
t_d-CK-DO	SCLK falling edge to next data valid delay	T_A in the range –40°C to 85°C		13.4	ns
		T_A in the range 0°C to 70°C		11.7
		T_A in the range 25°C to 50°C		10.7
t_d-CNV-DO	Enable time: CONVST low to MSB valid			12.3	ns
t_d-CNV-DOhz	Disable time: CONVST high or last SCLK falling edge to DOUT 3-state (CS mode)			13.2	ns
t_quiet	Quiet time	T_A in the range –40°C to 85°C	20		ns
t_quiet	Quiet time	T_A in the range 0°C to 70°C	13		ns

ADS8881C ADS8881I tim_3wire_op_bas547.gif

Figure 1. 3-Wire Operation: CONVST Functions as Chip Select

NOTE: Figure 1 shows the timing diagram for the 3-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 3-Wire Operation are also applicable for the 3-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.

7.7 Timing Requirements: 4-Wire Operation

All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted.

			MIN	MAX	UNIT
t_ACQ	Acquisition time		290		ns
t_conv	Conversion time	T_A in the range –40°C to 85°C	500	710	ns
t_conv	Conversion time	T_A in the range 0°C to 70°C	500	700	ns
t_conv	Conversion time		500		ns
1/f_sample	Time between conversions		1000		ns
t_wh-DI	Pulse duration: DIN high		10		ns
t_wl-CNV	Pulse width: CONVST low		20		ns
t_d-DI-DO	Delay time: DIN low to MSB valid			12.3	ns
t_d-DI-DOhz	Delay time: DIN high or last SCLK falling edge to DOUT 3-state			13.2	ns
t_su-DI-CNV	Setup time: DIN high to CONVST rising edge		7.5		ns
t_h-DI-CNV	Hold time: DIN high from CONVST rising edge (see Figure 63)		0		ns

ADS8881C ADS8881I tim_4wire_op_bas547.gif

Figure 2. 4-Wire Operation: DIN Functions as Chip Select

NOTE: Figure 2 shows the timing diagram for the 4-Wire CS Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: 4-Wire Operation are also applicable for the 4-Wire CS Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.

7.8 Timing Requirements: Daisy-Chain

All specifications are at AVDD = 3 V, DVDD = 3 V, and over the operating free-air temperature range, unless otherwise noted.

			MIN	MAX	UNIT
t_ACQ	Acquisition time		290		ns
t_conv	Conversion time	T_A in the range -40°C to 85°C	500	710	ns
t_conv	Conversion time	T_A in the range 0°C to 70°C	500	700	ns
t_conv	Conversion time		500		ns
1/f_sample	Time between conversions		1000		ns
t_su-CK-CNV	Setup time: SCLK valid to CONVST rising edge		5		ns
t_h-CK-CNV	Hold time: SCLK valid from CONVST rising edge		5		ns
t_su-DI-CNV	Setup time: DIN low to CONVST rising edge (see Figure 2)		7.5		ns
t_h-DI-CNV	Hold time: DIN low from CONVST rising edge (see Figure 63)		0		ns
t_su-DI-CK	Setup time: DIN valid to SCLK falling edge		1.5		ns

ADS8881C ADS8881I tim_daisy_op_bas547.gif

Figure 3. Daisy-Chain Operation: Two Devices

NOTE: Figure 3 shows the timing diagram for the Daisy-Chain Mode Without a Busy Indicator interface option. However, the timing parameters specified in Timing Requirements: Daisy-Chain are also applicable for the Daisy-Chain Mode With a Busy Indicator interface option, unless otherwise specified; see the Device Functional Modes section for specific details for each interface option.