8.1.2.1 Charge-Kickback Filter

The charge-kickback filter is an RC filter at the input pins of the ADC that filters the broadband noise from the front-end drive circuitry, and attenuates the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, C_FLT, is connected from each input pin of the ADC to the ground (as shown in Figure 104). This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. Generally, the value of this capacitor must be at least 20 times the specified value of the ADC sampling capacitance. For the ADS890xB, the input sampling capacitance is equal to 60 pF; therefore, for optimal performance, keep C_FLT greater than 1.2 nF. This capacitor must be a COG- or NPO-type. The type of dielectric used in COG or NPO ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.

Figure 104. Charge Kickback Filter Configuration

Driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (R_FLT) are used at the output of the amplifiers. A higher value of R_FLT helps with amplifier stability, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of R_FLT requires balancing the stability of the driver amplifier and distortion performance of the design. Always verify the stability and settling behavior of the driving amplifier and charge-kickback filter by TINA-TI™ SPICE simulation. Keep the tolerance of the selected resistors less than 1% to keep the inputs balanced.

8.1.2.2 Input Amplifier Selection

Selection criteria for the input amplifiers is highly dependent on the input signal type, as well as the performance goals, of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:

• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance of the amplifier, thus allowing the amplifier to more easily drive the ADC sample-and-hold capacitor and the RC filter (Charge-Kickback Filter) at the inputs of the ADC. Higher bandwidth amplifiers offer faster settling times while driving the capacitive load of the charge-kickback filter, thus reducing harmonic distortion at higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the amplifier with a unity gain bandwidth (UGB) as described in Equation 16:
Equation 16.
• Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. To make sure that the distortion performance of the data acquisition system is not limited by the front-end circuit, the distortion of the input driver must be at least 10 dB less than the distortion of the ADC, as shown in Equation 17.
Equation 17.
• Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in SNR performance of the system. Generally, to make sure that the noise performance of the data acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-limited by designing a low cutoff frequency, charge-kickback filter, as explained in Equation 18.
Equation 18.
where
• V_{1 / f_AMP_PP} is the peak-to-peak flicker noise in µV
• e_{n_RMS} is the amplifier broadband noise density in nV/√Hz
• f_–3dB is the 3-dB bandwidth of the charge-kickback filter
• N_G is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration
• Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal must settle within an 20-bit accuracy at the device inputs during the acquisition time window. This condition is critical to maintain the overall linearity performance of the ADC. Typically, amplifier data sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 20-bit accuracy. Therefore, always verify the settling behavior of the input driver by TINA-TI SPICE simulations before selecting the amplifier.

8.2.1.1 Design Requirements

For this example, the design parameters are listed in Table 21.

8.2.1.2 Detailed Design Procedure

The application circuit is illustrated in Figure 105. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.

The reference voltage of 4.5 V is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz.

Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The low-power OPA2625 (a high-bandwidth, low-distortion, high-precision amplifier in an inverting gain configuration) as an input driver provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications. The distortion resulting from variation in the common-mode signal is eliminated by using the OPA2625 in an inverting gain configuration. To exercise the complete dynamic range of the device, the common-mode voltage at the ADS890xB inputs is established at a value of 2.25 V (4.5 V / 2) by using the noninverting pins of the OPA2625 amplifiers. In addition, the components of the charge kickback filter keep the noise from the front-end circuit low without adding distortion to the input signal.

For a complete schematic, see the ADS8900BEVM-PDK user's guide located in the ADS8900B SAR Analog to Digital Converter Evaluation Module web folder at www.ti.com.

The same circuit is used in reference design TIPD211, a step-by-step process to design a 20-Bit, 1-MSPS, 4-Ch Small Form Factor Design for Test and Measurement Applications using four ADS8900B SAR ADCs, four OPA2625 precision amplifiers and one REF5050 precision reference.

	For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD211, 18-Bit, 1-MSPS, 4-Ch Small Form Factor Design for Test and Measurement Applications (TIDUBW7).

8.2.1.3 Application Curves

18-bit NMC DNL, ±1.5-ppm INL

Figure 106. Typical Linearity

fIN = 2 kHz, 101.8-dB SNR, –122-dB THD

Figure 108. Noise-Performance FFT Plot: ADS8902B

fIN = 2 kHz, 101.8-dB SNR, –122-dB THD

Figure 107. Noise-Performance FFT Plot: ADS8900B

fIN = 2 kHz, 101.8-dB SNR, –122-dB THD

Figure 109. Noise-Performance FFT Plot: ADS8904B

Table 22. Design Parameters