米6体育平台手机版

ZHCSF64B June 2016 – January 2018 ADS8910B , ADS8912B , ADS8914B

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGE|24
- MPQF124G

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND136Y

订购信息

6.7 Switching Characteristics

At RV_DD = 5.5 V, DV_DD = 1.65 V to 5.5 V, V_REF = 5 V, and maximum throughput (unless otherwise noted).
Minimum and maximum values at T_A = –40°C to +125°C; typical values at T_A = 25°C.

PARAMETER			MIN	TYP	MAX	UNIT	TIMING DIAGRAM
CONVERSION CYCLE
t_conv	Conversion time	ADS8910B	580		640	ns	Figure 1
		ADS8912B	1100		1200
		ADS8914B	2400		2500
ASYNCHRONOUS RESET, AND LOW POWER MODES
t_{d_rst}	Delay time: RST rising to RVS rising				3	ms	Figure 2
t_{PU_ADC}	Power-up time for converter module		1			ms	See PD_CNTL Register
t_{PU_REFBUF}	Power-up time for internal reference buffer, C_REFBUF = 22 µF		10			ms
t_{PU_Device}	Power-up time for device	C_LDO = 1 µF, C_REFBUF = 22 µF	10			ms
SPI-COMPATIBLE SERIAL INTERFACE
t_{den_CSDO}	Delay time: CS falling to data enable				9	ns	Figure 3
t_{dz_CSDO}	Delay time: CS rising to SDO going to Hi-Z				10	ns
t_{d_CKDO}	Delay time: SCLK launch edge to (next) data valid on SDO				13	ns
t_{d_CSRDY_f}	Delay time: CS falling to RVS falling				12	ns	Figure 4
t_{d_CSRDY_r}	Delay time: CS rising to RVS rising	After NOP operation			30	ns	Figure 4
t_{d_CSRDY_r}	Delay time: CS rising to RVS rising	After WR or RD operation			120	ns	Figure 4
SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)⁽¹⁾
t_{d_CKSTR_r}	Delay time: SCLK launch edge to RVS rising				13	ns	Figure 4
t_{d_CKSTR_f}	Delay time: SCLK launch edge to RVS falling				13	ns
t_{off_STRDO_f}	Time offset: RVS falling to (next) data valid on SDO		-2		2	ns
t_{off_STRDO_r}	Time offset: RVS rising to (next) data valid on SDO		-2		2	ns
t_{ph_STR}	Strobe output high time, 2.35 V ≤ DV_DD ≤ 5.5 V		0.45		0.55	t_STR
t_{pl_STR}	Strobe output low time, 2.35 V ≤ DV_DD ≤ 5.5 V		0.45		0.55	t_STR
SOURCE-SYNCHRONOUS SERIAL INTERFACE (Internal Clock)
t_{d_CSSTR}	Delay time: CS falling to RVS rising		15		50	ns	Figure 5
t_STR	Strobe output time period	INTCLK option		15		ns
		INTCLK / 2 option		30
		INTCLK / 4 option		60
t_{ph_STR}	Strobe output high time		0.45		0.55	t_STR
t_{pl_STR}	Strobe output low time		0.45		0.55	t_STR

ADS8910B ADS8912B ADS8914B ai_typ_conv_sbas707.gif

Figure 1. Conversion Cycle Timing

ADS8910B ADS8912B ADS8914B tim_reset_sbas707.gif

Figure 2. Asynchronous Reset Timing

ADS8910B ADS8912B ADS8914B tim_spi_sbas707.gif

1. The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.

Figure 3. SPI-Compatible Serial Interface Timing

ADS8910B ADS8912B ADS8914B tim_srcsync-extclk_sbas707.gif

Figure 4. Source-Synchronous Serial Interface Timing (External Clock)

ADS8910B ADS8912B ADS8914B tim_srcsync-intclk_sbas707.gif

Figure 5. Source-Synchronous Serial Interface Timing (Internal Clock)