ZHCSFE1B June   2016  – August 2017 ADS8920B , ADS8922B , ADS8924B

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      使用 ADS89xxB 集成功能轻松实现 系统设计
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. 7.3.3.1 Sample-and-Hold Circuit
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 7.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. 7.5.5.1 Single Device: All multiSPI Options
        2. 7.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.5.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. 7.6.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. 7.6.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. 7.6.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. 7.6.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. 7.6.1.6 PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. 7.6.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. 7.6.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. 7.6.1.9 REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 Documentation Support
      1. 11.1.1 相关文档
    2. 11.2 相关链接
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols

As shown in Table 5, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI-01-S, SPI-10-S, or SPI-11-S) to read data from the device.

Table 5. SPI Protocols for Reading From the Device

PROTOCOLSCLK POLARITY
(At CS Falling Edge)		SCLK PHASE
(Capture Edge)		MSB BIT LAUNCH EDGESDI_CNTLSDO_CNTLNO. OF SCLK
(Optimal Read Frame)		TIMING DIAGRAM
SPI-00-S Low Rising CS falling 00h 00h 16 Figure 56
SPI-01-S Low Falling 1st SCLK rising 01h 00h 16 Figure 57
SPI-10-S High Falling CS falling 02h 00h 16 Figure 58
SPI-11-S High Rising 1st SCLK falling 03h 00h 16 Figure 59

At power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data-read and data-write operations. To select a different SPI-compatible protocol for both the data transfer operations:

  1. Program the SDI_MODE[1:0] bits in the SDI_CNTL register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly selected protocol.
  2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CNTL register.

Figure 56 to Figure 59 explain the details of the four protocols using an optimal command frame to read all 22 bits of the output data word. Table 5 shows the number of SCLK required in an optimal read frame for the different output protocol selections.

ADS8920B ADS8922B ADS8924B SPI-00-1_bas707.gifFigure 56. SPI-00-S Protocol, 22 SCLKs
ADS8920B ADS8922B ADS8924B SPI-10-1_bas707.gifFigure 58. SPI-10-S Protocol, 22 SCLKs
ADS8920B ADS8922B ADS8924B SPI-01-1_bas707.gifFigure 57. SPI-01-S Protocol, 22 SCLKs
ADS8920B ADS8922B ADS8924B SPI-11-1_bas707.gifFigure 59. SPI-11-S Protocol, 22 SCLKs

For SDI_MODE[1:0] = 00b or 10b, the device supports an Early Data Launch (EDL) option. Set SDO_MODE[1:0] = 01b in the SDO_CNTL register to enable the feature (see Table 6). Setting SDO_MODE[1:0] = 01b has no effect if SDI_MODE[1:0] = 01b or 11b.

Table 6. SPI Protocols with Early Data Launch

PROTOCOLSCLK POLARITY
(At CS Falling Edge)		SCLK PHASE
(Capture Edge)		MSB BIT LAUNCH EDGESDI_CNTLSDO_CNTLNO. OF SCLK
(Optimal Read Frame)		TIMING DIAGRAM
SPI-00-S-EDL Low Rising CS falling 00h 01h 16 Figure 56
SPI-10-S-EDL High Falling CS falling 02h 01h 16 Figure 58

As shown in Figure 60, and Figure 61, the device launches the output data bit on the SDO-0 pin half clock earlier compared to the standard SPI protocol.

ADS8920B ADS8922B ADS8924B SPI-00-1-EDL_bas707.gifFigure 60. SPI-00-S-EDL Protocol, 22 SCLKs
ADS8920B ADS8922B ADS8924B SPI-10-1-EDL_bas707.gifFigure 61. SPI-10-S-EDL Protocol, 22 SCLKs

When using these SPI-compatible protocols, the RVS output remains low throughout the data transfer frame; see the Timing Requirements and Switching Characteristics tables for associated timing parameters.

With SDO_CNTL[7:0] = 00h or 01h, if the host controller uses a long data transfer frame, the device exhibits daisy-chain operation (see the Multiple Devices: Daisy-Chain Topology section).

NOTE

Use SPI-compatible protocols to execute the RD_REG, WR_REG, CLR_BITS, and SET_BITS commands specified in Table 2.
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