7.1 Overview

The device belongs to a family of dual, high-speed, simultaneous-sampling, analog-to-digital converters (ADCs). The device supports fully differential input signals and a full-scale input range equal to 2 × V_{REFP_x}.

When a conversion is initiated, the difference voltage between the AINP_x and AINM_x pins is sampled on the internal capacitor array. The device uses an internal clock to perform conversions. During the conversion process, both analog inputs are disconnected from the sampling capacitors. At the end of conversion process, the device reconnects the sampling capacitors to the AINP_x and AINM_x pins and enters an acquisition phase. The device has internal reference and reference buffers to provide the charge required by the ADCs during conversion. The device includes a reference voltage for the ADCs.

The enhanced serial programming interface (eSPI) digital interface is backward-compatible with traditional SPI protocols. eSPI configurable features simplify board layout, timing, and firmware and support high throughput at lower clock speeds, thus allowing an easy interface with a variety of microcontrollers, digital signal processors (DSPs), and field-programmable gate arrays (FPGAs). The device also provides a byte mode and a wide read cycle to reduce the clock frequency required for data transfer. The device includes a clock re-timer (CRT) to ensure data integrity when data are transferred through digital isolators. The device also supports double data rate (DDR) with SPI-compatible serial interface modes and with a clock re-timer.