Use a low-jitter external clock with a high slew rate to maximize SNR performance. The ADS981x can be operated with a differential or a single-ended clock input. Clock amplitude impacts the ADC aperture jitter and consequently the SNR. For maximum SNR performance, provide a clock signal with fast slew rates that maximizes swing between IOVDD and GND levels.

The sampling clock must be a free-running continuous clock. The ADC generates a valid output data, data clock, and frame clock t_{PU_SMPL_CLK}, as specified in the Switching Characteristics after a free-running sampling clock is applied. The ADC output data, data clock, and frame clock are invalid when the sampling clock is stopped.

Figure 6-4 shows a diagram of the differential sampling clock input. For this configuration, connect the differential sampling clock input to the SMPL_CLKP and SMPL_CLKM pins. Figure 6-5 shows a diagram of the single-ended sampling clock input. In this configuration, connect the single-ended sampling clock to SMPL_CLKP and connect SMPL_CLKM to ground.

Figure 6-4 AC-Coupled Differential Sampling Clock

Figure 6-5 Single-Ended Sampling Clock