ZHCSM18A January 2023 – December 2023 ADS9815 , ADS9817
PRODUCTION DATA
The ADS981x features a common-mode (CM) rejection circuit at the analog inputs that supports CM voltages up to ±12 V. The CM voltage for differential inputs is given by Equation 1. On power-up or after reset, the common-mode voltage range for the analog input channels is ±12 V (WIDE_CM_EN1 = 0b). Voltage at the analog inputs, in all cases, must be within the Absolute Maximum Ratings.
As described in Table 6-3, the CM voltage rejection circuit can be optimized for various CM voltages for differential inputs.
COMMON-MODE (CM) RANGE | CM_CTRL_EN | ADC A (ANALOG INPUT CHANNELS 1–4) |
ADC B (ANALOG INPUT CHANNELS 5–8) |
||
---|---|---|---|---|---|
CM_EN_ADC_A | CM_RNG_ADC_A [1:0] |
CM_EN_ADC_B | CM_RNG_ADC_B [1:0] |
||
CM ≤ ±1 V | 1 | 0 | Don't care | 0 | Don't care |
CM ≤ ±RANGE / 2 | 1 | 0 | 1 | 0 | |
CM ≤ ±6 V | 2 | 2 | |||
CM ≤ ±12 V | 1 | 1 |
The CM voltage rejection circuit must be configured depending on the analog input range of the PGA when using single-ended inputs as well. Table 6-4 lists the recommended configuration for single-ended inputs for various analog input voltage ranges.
PGA ANALOG INPUT RANGE | CM_CTRL_EN | ADC A (ANALOG INPUT CHANNELS 1–4) |
ADC B (ANALOG INPUT CHANNELS 5–8) |
||
---|---|---|---|---|---|
CM_EN_ADC_A | CM_RNG_ADC_A [1:0] |
CM_EN_ADC_B | CM_RNG_ADC_B [1:0] |
||
±2.5 V, ±3.5 V, and ±5 V | 1 | 0 | Don't care | 0 | Don't care |
±7 V, ±10 V, and ±12 V | 1 | 0 | 1 | 0 |