米6体育平台手机版

ZHCSM18A January 2023 – December 2023 ADS9815 , ADS9817

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RSH|56
- MPQF191C

散热焊盘机械数据 (封装 | 引脚)

RSH|56
- QFND099F

订购信息

6.3.6.1 Data Clock Output

The ADS981x features a source-synchronous data interface where the ADC provides the output data and the clock to capture the data. The clock to capture the data is output on the DCLKOUT pin. The clock frequency depends on the sampling clock speed, data rate (SDR or DDR), and number of output lanes (4-lanes or 2-lanes) and is given by Equation 3. The frame clock frequency is given by Equation 4.

Equation 3.

D a t a c l o c k f r e q u e n c y = \frac{24 b i t s / c h a n n e l \times 8 c h a n n e l s}{N u m b e r o f d a t a l a n e s \times D a t a r a t e (S D R = 1, D D R = 2)} \times S a m p l i n g c l o c k f r e q u e n c y

Equation 4.

Frame clock frequency = \frac{Sampling clock frequency}{4}

Table 6-8 shows the data clock frequency for the maximum sampling rates for the ADS9817 and ADS9815 for various interface modes.

Table 6-8 Data Clock Frequency for Interface Modes

INTERFACE MODE	ADS9815 (f_{SMPL_CLK} = 4 MHz)	ADS9817 (f_{SMPL_CLK} = 8 MHz)
4-lane, DDR	24 MHz	48 MHz
2-lane, DDR	48 MHz	96 MHz
4-lane, SDR	48 MHz	96 MHz
2-lane, SDR	96 MHz	Not supported